path: root/shared-core/nouveau_reg.h
AgeCommit message (Expand)AuthorFilesLines
2009-03-25nouveau: use PFB_CSTATUS naming from ddx (reg introduced with nv10)Stuart Bennett1-5/+3
2009-02-18nouveau: Add in-kernel backlight control supportMatthew Garrett1-0/+6
2008-12-10Revert "Merge branch 'modesetting-gem'"Jesse Barnes1-238/+2
2008-08-09NV50: enable hotplug irqMaarten Maathuis1-2/+0
2008-07-01NV50: some i2c cleanupMaarten Maathuis1-71/+11
2008-06-22NV50: Initial import of kernel modesetting.Maarten Maathuis1-0/+298
2008-04-05nv50: primitive i2c interrupt handlerMaarten Maathuis1-0/+3
2008-04-03nv50: primitive display interrupt handler.Maarten Maathuis1-0/+4
2008-02-16nv40: actually init all tile regs.Ben Skeggs1-12/+12
2008-02-02nouveau: NV40 can/should now be able to run after the blob.Maarten Maathuis1-0/+1
2008-01-04[PATCH] nouveau: reset AGP on init for < nv40Stuart Bennett1-0/+3
2007-11-14nouveau: Also wait until CACHE1 gets emptied.Ben Skeggs1-0/+1
2007-11-14nouveau: store user control reg offsets in channel structBen Skeggs1-9/+33
2007-11-14nouveau: funcs to determine active channel on PFIFO.Ben Skeggs1-0/+5
2007-11-05drm: remove lots of spurious whitespace.Dave Airlie1-1/+0
2007-10-10nouveau : nv10 and nv04 PGRAPH_NSTATUS are differentMatthieu Castet1-4/+8
2007-10-10nouveau: try to fix big endian.Stephane Marchesin1-0/+1
2007-09-30nouveau : nv20_graph replace nouveau_graph_wait_idle by nouveau_wait_for_idleMatthieu Castet1-3/+1
2007-09-10nouveau: nv10: add combiner registersPatrice Mandin1-0/+12
2007-08-26nouveau : add NV04_PGRAPH_TRAPPED_ADDR definitionMatthieu Castet1-3/+5
2007-08-22nouveau/nv40: Dump extra info on ucode state if ctx switch fails.Ben Skeggs1-0/+4
2007-08-10nouveau/nv50: demagic instmem setup.Ben Skeggs1-0/+10
2007-07-18nouveau: Add bitfield names for NSOURCE and NSTATUS.Pekka Paalanen1-0/+23
2007-07-18nouveau: Replace 0x00400104 and 0x00400108 with names.Pekka Paalanen1-0/+2
2007-07-11Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel.Arthur Huillet1-0/+2
2007-07-09nouveau/nv50: Initial channel/object supportBen Skeggs1-1/+11
2007-06-28nouveau: name some regsBen Skeggs1-0/+15
2007-06-24nouveau: NV04 PFIFO engtab functionsBen Skeggs1-1/+4
2007-06-24nouveau: NV4X PFIFO engtab functionsBen Skeggs1-2/+2
2007-04-06nouveau: make a note about a bit that breaks some cardsBen Skeggs1-0/+4
2007-03-26nouveau: move card initialisation into the drmBen Skeggs1-0/+53
2007-03-07nouveau: remove a hack that's not needed since the last interface change.Ben Skeggs1-2/+0
2007-02-28nouveau: intrusive drm interface changesBen Skeggs1-0/+8
2007-02-06nouveau: more work on the nv04 context switch code.Stephane Marchesin1-5/+7
2007-02-03nouveau: cleanup the nv04 pgraph save/restore mechanism.Stephane Marchesin1-0/+1
2007-02-03nouveau: rename registers to their proper names.Stephane Marchesin1-244/+249
2007-02-03nouveau: add NV04 registers required for PGRAPH context switching.Stephane Marchesin1-1/+54
2007-01-26nouveau: add extra pgraph registersPatrice Mandin1-0/+11
2007-01-13nouveau: nv20 graph ctx switch.Matthieu Castet1-0/+2
2007-01-13nouveau: add and indent pgraph regsMatthieu Castet1-15/+92
2007-01-13nouveau: Oops, fix the nv04 RAMFC_DMA_FETCH value.Stephane Marchesin1-1/+1
2007-01-12nouveau: get nv30 context switching to work.Jeremy Kolb1-0/+15
2007-01-06nouveau: Use PMC_BOOT_0 to determine which ctx_voodoo to load.Ben Skeggs1-0/+1
2007-01-05Cleanup the nv04 fifo code a bit.Stephane Marchesin1-0/+5
2006-11-28For nv10, bit 16 of RAMFC need to be set for 64 bytes fifo context.Matthieu Castet1-0/+1
2006-11-14Completely untested NV10/20/30 FIFO context switching changes.Ben Skeggs1-0/+14
2006-11-14Restructure initialisation a bit.Ben Skeggs1-0/+1
2006-11-06fixup fifo size so it is page alignedDave Airlie1-1/+1
2006-10-18Remove hack which delays activation of a additional channel. The previously ...Ben Skeggs1-0/+8
2006-10-17Useful output on a FIFO error interrupt.Ben Skeggs1-0/+5