diff options
| -rwxr-xr-x | amdgpu/amdgpu-symbol-check | 3 | ||||
| -rw-r--r-- | amdgpu/amdgpu.h | 54 | ||||
| -rw-r--r-- | amdgpu/amdgpu_bo.c | 34 | ||||
| -rw-r--r-- | amdgpu/amdgpu_cs.c | 25 |
4 files changed, 116 insertions, 0 deletions
diff --git a/amdgpu/amdgpu-symbol-check b/amdgpu/amdgpu-symbol-check index 6f5e0f95..96a44b40 100755 --- a/amdgpu/amdgpu-symbol-check +++ b/amdgpu/amdgpu-symbol-check @@ -19,6 +19,8 @@ amdgpu_bo_export amdgpu_bo_free amdgpu_bo_import amdgpu_bo_inc_ref +amdgpu_bo_list_create_raw +amdgpu_bo_list_destroy_raw amdgpu_bo_list_create amdgpu_bo_list_destroy amdgpu_bo_list_update @@ -47,6 +49,7 @@ amdgpu_query_sw_info amdgpu_cs_signal_semaphore amdgpu_cs_submit amdgpu_cs_submit_raw +amdgpu_cs_submit_raw2 amdgpu_cs_syncobj_export_sync_file amdgpu_cs_syncobj_import_sync_file amdgpu_cs_syncobj_reset diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h index dc51659a..d6de3b8d 100644 --- a/amdgpu/amdgpu.h +++ b/amdgpu/amdgpu.h @@ -42,6 +42,7 @@ extern "C" { #endif struct drm_amdgpu_info_hw_ip; +struct drm_amdgpu_bo_list_entry; /*--------------------------------------------------------------------------*/ /* --------------------------- Defines ------------------------------------ */ @@ -779,6 +780,37 @@ int amdgpu_bo_wait_for_idle(amdgpu_bo_handle buf_handle, * * \param dev - \c [in] Device handle. * See #amdgpu_device_initialize() + * \param number_of_buffers - \c [in] Number of BOs in the list + * \param buffers - \c [in] List of BO handles + * \param result - \c [out] Created BO list handle + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * + * \sa amdgpu_bo_list_destroy_raw(), amdgpu_cs_submit_raw2() +*/ +int amdgpu_bo_list_create_raw(amdgpu_device_handle dev, + uint32_t number_of_buffers, + struct drm_amdgpu_bo_list_entry *buffers, + uint32_t *result); + +/** + * Destroys a BO list handle. + * + * \param bo_list - \c [in] BO list handle. + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * + * \sa amdgpu_bo_list_create_raw(), amdgpu_cs_submit_raw2() +*/ +int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, uint32_t bo_list); + +/** + * Creates a BO list handle for command submission. + * + * \param dev - \c [in] Device handle. + * See #amdgpu_device_initialize() * \param number_of_resources - \c [in] Number of BOs in the list * \param resources - \c [in] List of BO handles * \param resource_prios - \c [in] Optional priority for each handle @@ -1587,6 +1619,28 @@ int amdgpu_cs_submit_raw(amdgpu_device_handle dev, struct drm_amdgpu_cs_chunk *chunks, uint64_t *seq_no); +/** + * Submit raw command submission to the kernel with a raw BO list handle. + * + * \param dev - \c [in] device handle + * \param context - \c [in] context handle for context id + * \param bo_list_handle - \c [in] raw bo list handle (0 for none) + * \param num_chunks - \c [in] number of CS chunks to submit + * \param chunks - \c [in] array of CS chunks + * \param seq_no - \c [out] output sequence number for submission. + * + * \return 0 on success\n + * <0 - Negative POSIX Error code + * + * \sa amdgpu_bo_list_create_raw(), amdgpu_bo_list_destroy_raw() + */ +int amdgpu_cs_submit_raw2(amdgpu_device_handle dev, + amdgpu_context_handle context, + uint32_t bo_list_handle, + int num_chunks, + struct drm_amdgpu_cs_chunk *chunks, + uint64_t *seq_no); + void amdgpu_cs_chunk_fence_to_dep(struct amdgpu_cs_fence *fence, struct drm_amdgpu_cs_chunk_dep *dep); void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, diff --git a/amdgpu/amdgpu_bo.c b/amdgpu/amdgpu_bo.c index c0f42e81..32ee358f 100644 --- a/amdgpu/amdgpu_bo.c +++ b/amdgpu/amdgpu_bo.c @@ -618,6 +618,40 @@ out: return r; } +drm_public int amdgpu_bo_list_create_raw(amdgpu_device_handle dev, + uint32_t number_of_buffers, + struct drm_amdgpu_bo_list_entry *buffers, + uint32_t *result) +{ + union drm_amdgpu_bo_list args; + int r; + + memset(&args, 0, sizeof(args)); + args.in.operation = AMDGPU_BO_LIST_OP_CREATE; + args.in.bo_number = number_of_buffers; + args.in.bo_info_size = sizeof(struct drm_amdgpu_bo_list_entry); + args.in.bo_info_ptr = (uint64_t)(uintptr_t)buffers; + + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST, + &args, sizeof(args)); + if (!r) + *result = args.out.list_handle; + return r; +} + +drm_public int amdgpu_bo_list_destroy_raw(amdgpu_device_handle dev, + uint32_t bo_list) +{ + union drm_amdgpu_bo_list args; + + memset(&args, 0, sizeof(args)); + args.in.operation = AMDGPU_BO_LIST_OP_DESTROY; + args.in.list_handle = bo_list; + + return drmCommandWriteRead(dev->fd, DRM_AMDGPU_BO_LIST, + &args, sizeof(args)); +} + drm_public int amdgpu_bo_list_create(amdgpu_device_handle dev, uint32_t number_of_resources, amdgpu_bo_handle *resources, diff --git a/amdgpu/amdgpu_cs.c b/amdgpu/amdgpu_cs.c index 3b8231aa..5bedf748 100644 --- a/amdgpu/amdgpu_cs.c +++ b/amdgpu/amdgpu_cs.c @@ -731,6 +731,31 @@ drm_public int amdgpu_cs_submit_raw(amdgpu_device_handle dev, return 0; } +drm_public int amdgpu_cs_submit_raw2(amdgpu_device_handle dev, + amdgpu_context_handle context, + uint32_t bo_list_handle, + int num_chunks, + struct drm_amdgpu_cs_chunk *chunks, + uint64_t *seq_no) +{ + union drm_amdgpu_cs cs = {0}; + uint64_t *chunk_array; + int i, r; + + chunk_array = alloca(sizeof(uint64_t) * num_chunks); + for (i = 0; i < num_chunks; i++) + chunk_array[i] = (uint64_t)(uintptr_t)&chunks[i]; + cs.in.chunks = (uint64_t)(uintptr_t)chunk_array; + cs.in.ctx_id = context->id; + cs.in.bo_list_handle = bo_list_handle; + cs.in.num_chunks = num_chunks; + r = drmCommandWriteRead(dev->fd, DRM_AMDGPU_CS, + &cs, sizeof(cs)); + if (!r && seq_no) + *seq_no = cs.out.handle; + return r; +} + drm_public void amdgpu_cs_chunk_fence_info_to_data(struct amdgpu_cs_fence_info *fence_info, struct drm_amdgpu_cs_chunk_data *data) { |