/* * Copyright 2020 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS IN THE SOFTWARE. * * */ #ifndef _mp_13_0_2_SH_MASK_HEADER #define _mp_13_0_2_SH_MASK_HEADER // addressBlock: mp_SmuMp0_SmnDec //MP0_SMN_C2PMSG_32 #define MP0_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_33 #define MP0_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_34 #define MP0_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_35 #define MP0_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_36 #define MP0_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_37 #define MP0_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_38 #define MP0_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_39 #define MP0_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_40 #define MP0_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_41 #define MP0_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_42 #define MP0_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_43 #define MP0_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_44 #define MP0_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_45 #define MP0_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_46 #define MP0_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_47 #define MP0_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_48 #define MP0_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_49 #define MP0_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_50 #define MP0_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_51 #define MP0_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_52 #define MP0_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_53 #define MP0_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_54 #define MP0_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_55 #define MP0_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_56 #define MP0_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_57 #define MP0_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_58 #define MP0_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_59 #define MP0_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_60 #define MP0_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_61 #define MP0_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_62 #define MP0_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_63 #define MP0_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_64 #define MP0_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_65 #define MP0_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_66 #define MP0_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_67 #define MP0_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_68 #define MP0_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_69 #define MP0_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_70 #define MP0_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_71 #define MP0_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_72 #define MP0_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_73 #define MP0_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_74 #define MP0_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_75 #define MP0_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_76 #define MP0_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_77 #define MP0_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_78 #define MP0_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_79 #define MP0_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_80 #define MP0_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_81 #define MP0_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_82 #define MP0_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_83 #define MP0_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_84 #define MP0_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_85 #define MP0_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_86 #define MP0_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_87 #define MP0_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_88 #define MP0_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_89 #define MP0_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_90 #define MP0_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_91 #define MP0_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_92 #define MP0_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_93 #define MP0_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_94 #define MP0_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_95 #define MP0_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_96 #define MP0_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_97 #define MP0_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_98 #define MP0_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_99 #define MP0_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_100 #define MP0_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_101 #define MP0_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_102 #define MP0_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_103 #define MP0_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_109 #define MP0_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 #define MP0_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL //MP0_SMN_C2PMSG_126 #define MP0_SMN_C2PMSG_126__GPU_ERR_MEM_TRAINING__SHIFT 0x0 #define MP0_SMN_C2PMSG_126__GPU_ERR_FW_LOAD__SHIFT 0x1 #define MP0_SMN_C2PMSG_126__GPU_ERR_WAFL_LINK_TRAINING__SHIFT 0x2 #define MP0_SMN_C2PMSG_126__GPU_ERR_XGMI_LINK_TRAINING__SHIFT 0x3 #define MP0_SMN_C2PMSG_126__GPU_ERR_USR_CP_LINK_TRAINING__SHIFT 0x4 #define MP0_SMN_C2PMSG_126__GPU_ERR_USR_DP_LINK_TRAINING__SHIFT 0x5 #define MP0_SMN_C2PMSG_126__GPU_ERR_HBM_MEM_TEST__SHIFT 0x6 #define MP0_SMN_C2PMSG_126__GPU_ERR_HBM_BIST_TEST__SHIFT 0x7 #define MP0_SMN_C2PMSG_126__SOCKET_ID__SHIFT 0x8 #define MP0_SMN_C2PMSG_126__AID_ID__SHIFT 0xb #define MP0_SMN_C2PMSG_126__HBM_ID__SHIFT 0xd #define MP0_SMN_C2PMSG_126__BOOT_STATUS__SHIFT 0x1f #define MP0_SMN_C2PMSG_126__GPU_ERR_MEM_TRAINING_MASK 0x00000001L #define MP0_SMN_C2PMSG_126__GPU_ERR_FW_LOAD_MASK 0x00000002L #define MP0_SMN_C2PMSG_126__GPU_ERR_WAFL_LINK_TRAINING_MASK 0x00000004L #define MP0_SMN_C2PMSG_126__GPU_ERR_XGMI_LINK_TRAINING_MASK 0x00000008L #define MP0_SMN_C2PMSG_126__GPU_ERR_USR_CP_LINK_TRAINING_MASK 0x00000010L #define MP0_SMN_C2PMSG_126__GPU_ERR_USR_DP_LINK_TRAINING_MASK 0x00000020L #define MP0_SMN_C2PMSG_126__GPU_ERR_HBM_MEM_TEST_MASK 0x00000040L #define MP0_SMN_C2PMSG_126__GPU_ERR_HBM_BIST_TEST_MASK 0x00000080L #define MP0_SMN_C2PMSG_126__SOCKET_ID_MASK 0x00000700L #define MP0_SMN_C2PMSG_126__AID_ID_MASK 0x00001800L #define MP0_SMN_C2PMSG_126__HBM_ID_MASK 0x00002000L #define MP0_SMN_C2PMSG_126__BOOT_STATUS_MASK 0x80000000L //MP0_SMN_IH_CREDIT #define MP0_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 #define MP0_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 #define MP0_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L #define MP0_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L //MP0_SMN_IH_SW_INT #define MP0_SMN_IH_SW_INT__ID__SHIFT 0x0 #define MP0_SMN_IH_SW_INT__VALID__SHIFT 0x8 #define MP0_SMN_IH_SW_INT__ID_MASK 0x000000FFL #define MP0_SMN_IH_SW_INT__VALID_MASK 0x00000100L //MP0_SMN_IH_SW_INT_CTRL #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 #define MP0_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L #define MP0_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L // addressBlock: mp_SmuMp1Pub_CruDec //MP1_FIRMWARE_FLAGS #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0 #define MP1_FIRMWARE_FLAGS__RESERVED__SHIFT 0x1 #define MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x00000001L #define MP1_FIRMWARE_FLAGS__RESERVED_MASK 0xFFFFFFFEL // addressBlock: mp_SmuMp1_SmnDec //MP1_SMN_C2PMSG_32 #define MP1_SMN_C2PMSG_32__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_32__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_33 #define MP1_SMN_C2PMSG_33__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_33__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_34 #define MP1_SMN_C2PMSG_34__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_34__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_35 #define MP1_SMN_C2PMSG_35__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_35__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_36 #define MP1_SMN_C2PMSG_36__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_36__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_37 #define MP1_SMN_C2PMSG_37__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_37__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_38 #define MP1_SMN_C2PMSG_38__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_38__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_39 #define MP1_SMN_C2PMSG_39__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_39__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_40 #define MP1_SMN_C2PMSG_40__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_40__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_41 #define MP1_SMN_C2PMSG_41__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_41__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_42 #define MP1_SMN_C2PMSG_42__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_42__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_43 #define MP1_SMN_C2PMSG_43__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_43__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_44 #define MP1_SMN_C2PMSG_44__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_44__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_45 #define MP1_SMN_C2PMSG_45__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_45__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_46 #define MP1_SMN_C2PMSG_46__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_46__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_47 #define MP1_SMN_C2PMSG_47__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_47__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_48 #define MP1_SMN_C2PMSG_48__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_48__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_49 #define MP1_SMN_C2PMSG_49__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_49__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_50 #define MP1_SMN_C2PMSG_50__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_50__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_51 #define MP1_SMN_C2PMSG_51__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_51__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_52 #define MP1_SMN_C2PMSG_52__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_52__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_53 #define MP1_SMN_C2PMSG_53__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_53__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_54 #define MP1_SMN_C2PMSG_54__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_54__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_55 #define MP1_SMN_C2PMSG_55__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_55__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_56 #define MP1_SMN_C2PMSG_56__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_56__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_57 #define MP1_SMN_C2PMSG_57__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_57__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_58 #define MP1_SMN_C2PMSG_58__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_58__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_59 #define MP1_SMN_C2PMSG_59__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_59__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_60 #define MP1_SMN_C2PMSG_60__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_60__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_61 #define MP1_SMN_C2PMSG_61__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_61__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_62 #define MP1_SMN_C2PMSG_62__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_62__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_63 #define MP1_SMN_C2PMSG_63__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_63__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_64 #define MP1_SMN_C2PMSG_64__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_64__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_65 #define MP1_SMN_C2PMSG_65__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_65__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_66 #define MP1_SMN_C2PMSG_66__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_66__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_67 #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_67__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_68 #define MP1_SMN_C2PMSG_68__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_68__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_69 #define MP1_SMN_C2PMSG_69__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_69__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_70 #define MP1_SMN_C2PMSG_70__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_70__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_71 #define MP1_SMN_C2PMSG_71__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_71__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_72 #define MP1_SMN_C2PMSG_72__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_72__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_73 #define MP1_SMN_C2PMSG_73__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_73__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_74 #define MP1_SMN_C2PMSG_74__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_74__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_75 #define MP1_SMN_C2PMSG_75__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_75__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_76 #define MP1_SMN_C2PMSG_76__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_76__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_77 #define MP1_SMN_C2PMSG_77__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_77__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_78 #define MP1_SMN_C2PMSG_78__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_78__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_79 #define MP1_SMN_C2PMSG_79__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_79__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_80 #define MP1_SMN_C2PMSG_80__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_80__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_81 #define MP1_SMN_C2PMSG_81__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_81__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_82 #define MP1_SMN_C2PMSG_82__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_82__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_83 #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_83__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_84 #define MP1_SMN_C2PMSG_84__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_84__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_85 #define MP1_SMN_C2PMSG_85__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_85__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_86 #define MP1_SMN_C2PMSG_86__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_86__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_87 #define MP1_SMN_C2PMSG_87__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_87__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_88 #define MP1_SMN_C2PMSG_88__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_88__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_89 #define MP1_SMN_C2PMSG_89__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_89__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_90 #define MP1_SMN_C2PMSG_90__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_90__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_91 #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_91__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_92 #define MP1_SMN_C2PMSG_92__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_92__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_93 #define MP1_SMN_C2PMSG_93__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_93__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_94 #define MP1_SMN_C2PMSG_94__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_94__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_95 #define MP1_SMN_C2PMSG_95__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_95__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_96 #define MP1_SMN_C2PMSG_96__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_96__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_97 #define MP1_SMN_C2PMSG_97__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_97__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_98 #define MP1_SMN_C2PMSG_98__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_98__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_99 #define MP1_SMN_C2PMSG_99__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_99__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_100 #define MP1_SMN_C2PMSG_100__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_100__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_101 #define MP1_SMN_C2PMSG_101__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_101__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_102 #define MP1_SMN_C2PMSG_102__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_102__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_103 #define MP1_SMN_C2PMSG_103__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_103__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_104 #define MP1_SMN_C2PMSG_104__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_104__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_105 #define MP1_SMN_C2PMSG_105__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_105__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_106 #define MP1_SMN_C2PMSG_106__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_106__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_107 #define MP1_SMN_C2PMSG_107__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_107__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_108 #define MP1_SMN_C2PMSG_108__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_108__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_109 #define MP1_SMN_C2PMSG_109__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_109__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_110 #define MP1_SMN_C2PMSG_110__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_110__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_111 #define MP1_SMN_C2PMSG_111__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_111__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_112 #define MP1_SMN_C2PMSG_112__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_112__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_113 #define MP1_SMN_C2PMSG_113__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_113__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_114 #define MP1_SMN_C2PMSG_114__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_114__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_115 #define MP1_SMN_C2PMSG_115__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_115__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_116 #define MP1_SMN_C2PMSG_116__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_116__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_117 #define MP1_SMN_C2PMSG_117__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_117__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_118 #define MP1_SMN_C2PMSG_118__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_118__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_119 #define MP1_SMN_C2PMSG_119__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_119__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_120 #define MP1_SMN_C2PMSG_120__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_120__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_121 #define MP1_SMN_C2PMSG_121__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_121__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_122 #define MP1_SMN_C2PMSG_122__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_122__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_123 #define MP1_SMN_C2PMSG_123__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_123__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_124 #define MP1_SMN_C2PMSG_124__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_124__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_125 #define MP1_SMN_C2PMSG_125__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_125__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_126 #define MP1_SMN_C2PMSG_126__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_126__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_C2PMSG_127 #define MP1_SMN_C2PMSG_127__CONTENT__SHIFT 0x0 #define MP1_SMN_C2PMSG_127__CONTENT_MASK 0xFFFFFFFFL //MP1_SMN_IH_CREDIT #define MP1_SMN_IH_CREDIT__CREDIT_VALUE__SHIFT 0x0 #define MP1_SMN_IH_CREDIT__CLIENT_ID__SHIFT 0x10 #define MP1_SMN_IH_CREDIT__CREDIT_VALUE_MASK 0x00000003L #define MP1_SMN_IH_CREDIT__CLIENT_ID_MASK 0x00FF0000L //MP1_SMN_IH_SW_INT #define MP1_SMN_IH_SW_INT__ID__SHIFT 0x0 #define MP1_SMN_IH_SW_INT__VALID__SHIFT 0x8 #define MP1_SMN_IH_SW_INT__ID_MASK 0x000000FFL #define MP1_SMN_IH_SW_INT__VALID_MASK 0x00000100L //MP1_SMN_IH_SW_INT_CTRL #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK__SHIFT 0x0 #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK__SHIFT 0x8 #define MP1_SMN_IH_SW_INT_CTRL__INT_MASK_MASK 0x00000001L #define MP1_SMN_IH_SW_INT_CTRL__INT_ACK_MASK 0x00000100L //MP1_SMN_FPS_CNT #define MP1_SMN_FPS_CNT__COUNT__SHIFT 0x0 #define MP1_SMN_FPS_CNT__COUNT_MASK 0xFFFFFFFFL //MP1_SMN_EXT_SCRATCH0 #define MP1_SMN_EXT_SCRATCH0__DATA__SHIFT 0x0 #define MP1_SMN_EXT_SCRATCH0__DATA_MASK 0xFFFFFFFFL //MP1_SMN_EXT_SCRATCH1 #define MP1_SMN_EXT_SCRATCH1__DATA__SHIFT 0x0 #define MP1_SMN_EXT_SCRATCH1__DATA_MASK 0xFFFFFFFFL //MP1_SMN_EXT_SCRATCH2 #define MP1_SMN_EXT_SCRATCH2__DATA__SHIFT 0x0 #define MP1_SMN_EXT_SCRATCH2__DATA_MASK 0xFFFFFFFFL //MP1_SMN_EXT_SCRATCH3 #define MP1_SMN_EXT_SCRATCH3__DATA__SHIFT 0x0 #define MP1_SMN_EXT_SCRATCH3__DATA_MASK 0xFFFFFFFFL //MP1_SMN_EXT_SCRATCH4 #define MP1_SMN_EXT_SCRATCH4__DATA__SHIFT 0x0 #define MP1_SMN_EXT_SCRATCH4__DATA_MASK 0xFFFFFFFFL //MP1_SMN_EXT_SCRATCH5 #define MP1_SMN_EXT_SCRATCH5__DATA__SHIFT 0x0 #define MP1_SMN_EXT_SCRATCH5__DATA_MASK 0xFFFFFFFFL //MP1_SMN_EXT_SCRATCH6 #define MP1_SMN_EXT_SCRATCH6__DATA__SHIFT 0x0 #define MP1_SMN_EXT_SCRATCH6__DATA_MASK 0xFFFFFFFFL //MP1_SMN_EXT_SCRATCH7 #define MP1_SMN_EXT_SCRATCH7__DATA__SHIFT 0x0 #define MP1_SMN_EXT_SCRATCH7__DATA_MASK 0xFFFFFFFFL #endif