From b4d5ce7a5024094430d3b9a061710fccb49ba884 Mon Sep 17 00:00:00 2001 From: Brandon Syu Date: Mon, 8 Jun 2020 14:01:57 +0800 Subject: drm/amd/display: use dispclk AVFS for dppclk [Why] There is using pixelclk AVFS for dppclk, that would cause issue. [How] To use dispclk AVFS for both dispclk and dppclk. There would choose dppclk for request voltage when dispclk wouldn't be updated case. If dispclk need to be updated, then it'll choose the bigger one from dppclk and dispclk for request voltage. Signed-off-by: Brandon Syu Reviewed-by: Tony Cheng Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- .../drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 18 +++++++++++++----- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 2 files changed, 14 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display') diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c index 55d09adbf0d9..c63ec960e116 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c @@ -234,20 +234,26 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base, dpp_clock_lowered = true; clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz; - if (pp_smu && pp_smu->set_voltage_by_freq) - pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_PIXELCLK, clk_mgr_base->clks.dppclk_khz / 1000); - update_dppclk = true; } if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; - if (pp_smu && pp_smu->set_voltage_by_freq) - pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.dispclk_khz / 1000); update_dispclk = true; } + if (update_dppclk || update_dispclk) { + new_clocks->disp_dpp_voltage_level_khz = new_clocks->dppclk_khz; + + if (update_dispclk) + new_clocks->disp_dpp_voltage_level_khz = new_clocks->dispclk_khz > new_clocks->dppclk_khz ? new_clocks->dispclk_khz : new_clocks->dppclk_khz; + + clk_mgr_base->clks.disp_dpp_voltage_level_khz = new_clocks->disp_dpp_voltage_level_khz; + if (pp_smu && pp_smu->set_voltage_by_freq) + pp_smu->set_voltage_by_freq(&pp_smu->pp_smu, PP_SMU_NV_DISPCLK, clk_mgr_base->clks.disp_dpp_voltage_level_khz / 1000); + } + if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) { if (dpp_clock_lowered) { // if clock is being lowered, increase DTO before lowering refclk @@ -403,6 +409,8 @@ static bool dcn2_are_clock_states_equal(struct dc_clocks *a, return false; else if (a->dppclk_khz != b->dppclk_khz) return false; + else if (a->disp_dpp_voltage_level_khz != b->disp_dpp_voltage_level_khz) + return false; else if (a->dcfclk_khz != b->dcfclk_khz) return false; else if (a->socclk_khz != b->socclk_khz) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f9eb8c37d7c3..83de4c2e045e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -337,6 +337,7 @@ enum dcn_pwr_state { struct dc_clocks { int dispclk_khz; int dppclk_khz; + int disp_dpp_voltage_level_khz; int dcfclk_khz; int socclk_khz; int dcfclk_deep_sleep_khz; -- cgit v1.2.3