From 0126abd4d13f71e41fd5b08bea0b44a6b2c186a9 Mon Sep 17 00:00:00 2001 From: Aaron Liu Date: Wed, 24 Jul 2019 13:53:17 -0500 Subject: drm/amdgpu: fix no interrupt issue for renoir emu In renoir's ih model, there's a change in mmIH_CHICKEN register, that limits IH to use physical address directly. Those chicken bits need to be programmed first. Acked-by: Huang Rui Signed-off-by: Aaron Liu Reviewed-by: Huang Rui Reviewed-by: Hawking Zhang Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/amdgpu/vega10_ih.c') diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index c1c0a39ae269..4fac1e91a054 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -247,7 +247,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) WREG32_SOC15(OSSSYS, 0, mmIH_RB_CNTL, ih_rb_cntl); } - if (adev->asic_type == CHIP_ARCTURUS && + if ((adev->asic_type == CHIP_ARCTURUS || adev->asic_type == CHIP_RENOIR) && adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { if (adev->irq.ih.use_bus_addr) { ih_chicken = RREG32_SOC15(OSSSYS, 0, mmIH_CHICKEN); -- cgit v1.2.3