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path: root/drivers/gpu/ipu-v3/ipu-pre.c
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2018-02-19gpu: ipu-v3: pre: fix device node leak in ipu_pre_lookup_by_phandleTobias Jordan1-0/+3
Before returning, call of_node_put() for the device node returned by of_parse_phandle(). Fixes: d2a34232580a ("gpu: ipu-v3: add driver for Prefetch Resolve Engine") Signed-off-by: Tobias Jordan <Tobias.Jordan@elektrobit.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-12-19gpu: ipu-v3: pre: add tiled prefetch supportLucas Stach1-3/+26
This configures the TPR unit, using the DRM format modifier. For now only the single buffer modifiers are supported, as split buffer needs more configuration for the required cropping. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> [p.zabel@pengutronix.de: rebased after ERR009624 workaround] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-10-11gpu: ipu-v3: pre: implement workaround for ERR009624Lucas Stach1-0/+29
The PRE has a bug where a software write to the CTRL register can block the setting of the ENABLE bit by the hardware in auto repeat mode. When this happens the PRE will fail to handle new jobs. To work around this software must not write to CTRL register when the PRE store engine is inside the unsafe window, where a hardware update to the ENABLE bit may happen. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> [p.zabel@pengutronix.de: rebased before PRE tiled prefetch support] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-06-06gpu: ipu-v3: pre: only use internal clock gatingLucas Stach1-8/+5
By setting the SFTRST bit, the PRE will be held in the lowest power state with clocks to the internal blocks gated. When external clock gating is used (from the external clock controller, or by setting the CLKGATE bit) the PRE will sporadically fail to start. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Fixes: d2a34232580a ("gpu: ipu-v3: add driver for Prefetch Resolve Engine") Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
2017-03-15gpu: ipu-v3: add driver for Prefetch Resolve EngineLucas Stach1-0/+289
This adds support for the i.MX6 QuadPlus PRE units. Currently only linear prefetch into SRAM is supported, other modes of operation like the tiled-to-linear conversion will be added later. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>