path: root/drivers/gpu/ipu-v3/ipu-di.c
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2016-11-09gpu: ipu-di: silence videomode logspamLucas Stach1-1/+1
Adapting the videomode to the hardware constraints is something that can and must happen during normal operation and isn't something that the user can avoid. So printing a warning each time it happens isn't helpful. Demote this message to the debug level. Signed-off-by: Lucas Stach <> Signed-off-by: Philipp Zabel <>
2016-07-12drm/imx: atomic phase 1: Use transitional atomic CRTC and plane helpersLiu Ying1-3/+0
Use the drm_plane_helper_update/disable() and drm_helper_crtc_mode_set() transitional atomic helpers. The crtc->mode_set_nofb callback is added so that the primary plane is no longer tied to the CRTC. Check/update logics are separated to make sure crtc->mode_set_nofb and plane->atomic_update are always successful. Also, some necessary logics are tweaked for a smooth transition. Signed-off-by: Liu Ying <> Acked-by: Daniel Vetter <> Signed-off-by: Philipp Zabel <>
2015-10-06gpu: imx: fix support for interlaced modesRussell King1-42/+37
The support for interlaced video modes seems to be broken; we don't use anything other than the vtotal/htotal from the timing information to define the various sync counters. Freescale patches for interlaced video support contain an alternative sync counter setup, which we include here. This setup produces the hsync and vsync via the normal counter 2 and 3, but moves the display enable signal from counter 5 to counter 6. Therefore, we need to change the display controller setup as well. The corresponding Freescale patches for this change are: iMX6-HDMI-support-interlaced-display-mode.patch IPU-fine-tuning-the-interlace-display-timing-for-CEA.patch This produces a working interlace format output from the IPU. Tested-by: Philipp Zabel <> Reviewed-by: Fabio Estevam <> Signed-off-by: Russell King <>
2015-10-06gpu: imx: simplify sync polarity settingRussell King1-22/+28
Use a function to convert the sync pin to a bit mask for the DI_GENERAL register, and move this out of the interlace/non-interlace path to the common path. Tested-by: Philipp Zabel <> Reviewed-by: Fabio Estevam <> Signed-off-by: Russell King <>
2015-03-31gpu: ipu-v3: limit pixel clock divider to 8-bitsPhilipp Zabel1-6/+3
The DI pixel clock divider bit field is only 8 bits wide for the integer part, so limit the divider to the 1...255 interval before deciding whether the internal clock can be used and before writing to the register. Reported-by: Felix Mellmann <> Signed-off-by: Philipp Zabel <>
2015-02-23gpu: ipu-v3: do not divide by zero if the pixel clock is too largePhilipp Zabel1-0/+2
Even if an unsupported mode with a pixel clock larger than two times the 264 MHz IPU HSP clock is set, don't divide by zero. Signed-off-by: Philipp Zabel <>
2015-01-07gpu: ipu-di: Switch to DIV_ROUND_CLOSEST for DI clock divider calcSteve Longerbeam1-6/+3
We can use the DIV_ROUND_CLOSEST() macro when calculating the DI clock divider, rounded to nearest int. Suggested-by: Philipp Zabel <> Signed-off-by: Steve Longerbeam <> Signed-off-by: Philipp Zabel <>
2015-01-07gpu: ipu-v3: Use videomode in struct ipu_di_signal_cfgSteve Longerbeam1-41/+48
This patch changes struct ipu_di_signal_cfg to use struct videomode to define video timings and flags. Signed-off-by: Steve Longerbeam <> Signed-off-by: Philipp Zabel <>
2015-01-07gpu: ipu-di: remove some non-functional codeSteve Longerbeam1-6/+0
h_total and v_total were calculated in ipu_di_init_sync_panel() but never actually used. Remove. Signed-off-by: Steve Longerbeam <> Signed-off-by: Philipp Zabel <>
2015-01-07gpu: ipu-di: Add ipu_di_adjust_videomode()Jiada Wang1-0/+29
On some monitors, high resolution modes are not working, exhibiting pixel column truncation problems (for example, 1280x1024 displays as 1280x1022). The function ipu_di_adjust_videomode() aims to fix these issues by adjusting a passed videomode to IPU restrictions. The function can be called from the drm_crtc_helper_funcs->mode_fixup() methods. Signed-off-by: Jiada Wang <> Signed-off-by: Deepak Das <> Signed-off-by: Steve Longerbeam <> Signed-off-by: Philipp Zabel <>
2014-06-12Merge branch 'drm-next' of git:// Torvalds1-0/+730
Pull drm updates from Dave Airlie: "This is the main drm merge window pull request, changes all over the place, mostly normal levels of churn. Highlights: Core drm: More cleanups, fix race on connector/encoder naming, docs updates, object locking rework in prep for atomic modeset i915: mipi DSI support, valleyview power fixes, cursor size fixes, execlist refactoring, vblank improvements, userptr support, OOM handling improvements radeon: GPUVM tuning and large page size support, gart fixes, deep color HDMI support, HDMI audio cleanups nouveau: - displayport rework should fix lots of issues - initial gk20a support - gk110b support - gk208 fixes exynos: probe order fixes, HDMI changes, IPP consolidation msm: debugfs updates, misc fixes ast: ast2400 support, sync with UMS driver tegra: cleanups, hdmi + hw cursor for Tegra 124. panel: fixes existing panels add some new ones. ipuv3: moved from staging to drivers/gpu" * 'drm-next' of git:// (761 commits) drm/nouveau/disp/dp: fix tmds passthrough on dp connector drm/nouveau/dp: probe dpcd to determine connectedness drm/nv50-: trigger update after all connectors disabled drm/nv50-: prepare for attaching a SOR to multiple heads drm/gf119-/disp: fix debug output on update failure drm/nouveau/disp/dp: make use of postcursor when its available drm/g94-/disp/dp: take max pullup value across all lanes drm/nouveau/bios/dp: parse lane postcursor data drm/nouveau/dp: fix support for dpms drm/nouveau: register a drm_dp_aux channel for each dp connector drm/g94-/disp: add method to power-off dp lanes drm/nouveau/disp/dp: maintain link in response to hpd signal drm/g94-/disp: bash and wait for something after changing lane power regs drm/nouveau/disp/dp: split link config/power into two steps drm/nv50/disp: train PIOR-attached DP from second supervisor drm/nouveau/disp/dp: make use of existing output data for link training drm/gf119/disp: start removing direct vbios parsing from supervisor drm/nv50/disp: start removing direct vbios parsing from supervisor drm/nouveau/disp/dp: maintain receiver caps in response to hpd signal drm/nouveau/disp/dp: create subclass for dp outputs ...
2014-06-04gpu: ipu-v3: Move i.MX IPUv3 core driver out of stagingPhilipp Zabel1-0/+730
The i.MX Image Processing Unit (IPU) contains a number of image processing blocks that sit right in the middle between DRM and V4L2. Some of the modules, such as Display Controller, Processor, and Interface (DC, DP, DI) or CMOS Sensor Interface (CSI) and their FIFOs could be assigned to either framework, but others, such as the dma controller (IDMAC) and image converter (IC) can be used by both. The IPUv3 core driver provides an internal API to access the modules, to be used by both DRM and V4L2 IPUv3 drivers. Signed-off-by: Lucas Stach <> Signed-off-by: Philipp Zabel <> Acked-by: Greg Kroah-Hartman <>