drm/drm - DRM kernel graphics driver development tree

Age	Commit message (Expand)	Author	Files	Lines
2020-02-13	drm/msm/dsi/pll: call vco set rate explicitly	Harigovindan P	1	-0/+6
2020-01-06	clk: mux: Add support for specifying parents via DT/pointers	Stephen Boyd	2	-4/+4
2019-09-03	drm/msm: drop use of drmP.h	Sam Ravnborg	1	-1/+1
2019-06-28	Merge tag 'drm-msm-next-2019-06-25' of https://gitlab.freedesktop.org/drm/msm...	Dave Airlie	1	-33/+73
2019-06-20	drm/msm/dsi_pll_10nm: Remove impossible check	Sean Paul	1	-3/+0
2019-06-20	drm/msm/dsi_pll_10nm: Release clk hw on destroy and failure	Sean Paul	1	-30/+73
2019-06-05	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284	Thomas Gleixner	5	-45/+5
2018-12-25	Merge tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm	Linus Torvalds	5	-28/+28
2018-12-11	drm/msm/dsi: fix dsi clock names in DSI 10nm PLL driver	Abhinav Kumar	1	-4/+4
2018-12-11	drm: msm: Use DRM_DEV_* instead of dev_*	Mamta Shukla	5	-24/+24
2018-11-30	drm/msm/dsi: configure VCO rate for 10nm PLL driver	Abhinav Kumar	1	-1/+3
2018-07-26	drm/msm/dsi: initialize postdiv_lock before use for 10nm pll	Rajesh Yadav	1	-0/+2
2018-02-20	drm/msm/dsi: Populate PLL 10nm clock ops	Archit Taneja	1	-8/+654
2018-02-20	drm/msm/dsi: Add skeleton 10nm PHY/PLL code	Archit Taneja	3	-0/+188
2018-02-20	drm/msm/dsi: check for failure on retrieving pll in dsi manager	Lloyd Atkinson	1	-1/+1
2017-12-28	clk: divider: fix incorrect usage of container_of	Jerome Brunet	1	-1/+1
2017-02-06	drm/msm/dsi: Add PHY/PLL for 8x96	Archit Taneja	3	-0/+1127
2016-11-02	drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocks	Archit Taneja	2	-0/+2
2016-03-03	drm/msm/dsi: fix definition of msm_dsi_pll_28nm_8960_init()	Luis Henriques	1	-2/+2
2015-12-14	drm/msm/dsi: Add DSI PLL for 28nm 8960 PHY	Archit Taneja	3	-0/+546
2015-09-04	Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux	Linus Torvalds	3	-36/+46
2015-08-24	drm/msm/dsi: Convert to clk_hw based provider APIs	Stephen Boyd	1	-2/+2
2015-08-15	drm/msm/dsi: Make each PHY type compilation independent	Hai Li	1	-0/+8
2015-08-15	drm/msm/dsi: Save/Restore PLL status across PHY reset	Hai Li	3	-36/+38
2015-06-11	drm/msm/dsi: Add DSI PLL clock driver support	Hai Li	3	-0/+905