path: root/drivers/gpu/drm/msm/dsi/pll
AgeCommit message (Expand)AuthorFilesLines
2020-02-13drm/msm/dsi/pll: call vco set rate explicitlyHarigovindan P1-0/+6
2020-01-06clk: mux: Add support for specifying parents via DT/pointersStephen Boyd2-4/+4
2019-09-03drm/msm: drop use of drmP.hSam Ravnborg1-1/+1
2019-06-28Merge tag 'drm-msm-next-2019-06-25' of Airlie1-33/+73
2019-06-20drm/msm/dsi_pll_10nm: Remove impossible checkSean Paul1-3/+0
2019-06-20drm/msm/dsi_pll_10nm: Release clk hw on destroy and failureSean Paul1-30/+73
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 284Thomas Gleixner5-45/+5
2018-12-25Merge tag 'drm-next-2018-12-14' of git:// Torvalds5-28/+28
2018-12-11drm/msm/dsi: fix dsi clock names in DSI 10nm PLL driverAbhinav Kumar1-4/+4
2018-12-11drm: msm: Use DRM_DEV_* instead of dev_*Mamta Shukla5-24/+24
2018-11-30drm/msm/dsi: configure VCO rate for 10nm PLL driverAbhinav Kumar1-1/+3
2018-07-26drm/msm/dsi: initialize postdiv_lock before use for 10nm pllRajesh Yadav1-0/+2
2018-02-20drm/msm/dsi: Populate PLL 10nm clock opsArchit Taneja1-8/+654
2018-02-20drm/msm/dsi: Add skeleton 10nm PHY/PLL codeArchit Taneja3-0/+188
2018-02-20drm/msm/dsi: check for failure on retrieving pll in dsi managerLloyd Atkinson1-1/+1
2017-12-28clk: divider: fix incorrect usage of container_ofJerome Brunet1-1/+1
2017-02-06drm/msm/dsi: Add PHY/PLL for 8x96Archit Taneja3-0/+1127
2016-11-02drm/msm: Set CLK_IGNORE_UNUSED flag for PLL clocksArchit Taneja2-0/+2
2016-03-03drm/msm/dsi: fix definition of msm_dsi_pll_28nm_8960_init()Luis Henriques1-2/+2
2015-12-14drm/msm/dsi: Add DSI PLL for 28nm 8960 PHYArchit Taneja3-0/+546
2015-09-04Merge branch 'drm-next' of git:// Torvalds3-36/+46
2015-08-24drm/msm/dsi: Convert to clk_hw based provider APIsStephen Boyd1-2/+2
2015-08-15drm/msm/dsi: Make each PHY type compilation independentHai Li1-0/+8
2015-08-15drm/msm/dsi: Save/Restore PLL status across PHY resetHai Li3-36/+38
2015-06-11drm/msm/dsi: Add DSI PLL clock driver supportHai Li3-0/+905