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path: root/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
AgeCommit message (Expand)AuthorFilesLines
2020-04-13soc / drm: mediatek: Move routing control to mmsys deviceEnric Balletbo i Serra1-256/+0
2020-04-13drm/mediatek: Omit warning on probe defersMatthias Brugger1-1/+2
2019-10-09drm/mediatek: add no_clk into ddp private dataCK Hu1-6/+9
2019-10-09drm/mediatek: add mutex sof register offset into ddp private dataYongqiang Niu1-3/+10
2019-10-09drm/mediatek: add mutex sof into ddp private dataYongqiang Niu1-8/+35
2019-10-09drm/mediatek: add mutex mod register offset into ddp private dataYongqiang Niu1-8/+16
2019-10-09drm/mediatek: add mutex mod into ddp private dataYongqiang Niu1-11/+30
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-9/+1
2018-10-03drm/mediatek: implement connection from BLS to DPI0Bibby Hsieh1-1/+13
2018-08-27drm/mediatek: fix connection from RDMA2 to DSI1Stu Hsieh1-1/+1
2018-08-27drm/mediatek: add connection from RDMA2 to DSI0Stu Hsieh1-0/+4
2018-08-27drm/mediatek: add connection from RDMA1 to DSI0Stu Hsieh1-0/+4
2018-08-27drm/mediatek: add connection from RDMA0 to DSI1Stu Hsieh1-0/+4
2018-08-27drm/mediatek: add connection from RDMA0 to DPI1Stu Hsieh1-0/+4
2018-06-28drm/mediatek: Add support for mediatek SOC MT2712stu.hsieh@mediatek.com1-0/+39
2018-06-24drm/mediatek: add DSI3 support for mutexstu.hsieh@mediatek.com1-0/+5
2018-06-24drm/mediatek: add DSI2 support for mutexstu.hsieh@mediatek.com1-0/+5
2018-06-24drm/mediatek: add DPI1 support for mutexstu.hsieh@mediatek.com1-0/+5
2018-06-24drm/mediatek: add connection from RDMA2 to DSI3stu.hsieh@mediatek.com1-0/+8
2018-06-24drm/mediatek: add connection from RDMA2 to DSI2stu.hsieh@mediatek.com1-0/+8
2018-06-24drm/mediatek: add connection from RDMA2 to DSI1stu.hsieh@mediatek.com1-0/+8
2018-06-24drm/mediatek: add connection from RDMA2 to DPI1stu.hsieh@mediatek.com1-0/+8
2018-06-24drm/mediatek: add connection from RDMA2 to DPI0stu.hsieh@mediatek.com1-0/+9
2018-06-24drm/mediatek: add connection from RDMA1 to DSI3stu.hsieh@mediatek.com1-0/+8
2018-06-24drm/mediatek: add connection from RDMA1 to DSI2stu.hsieh@mediatek.com1-0/+9
2018-06-24drm/mediatek: add connection from RDMA1 to DSI1stu.hsieh@mediatek.com1-0/+9
2018-06-24drm/mediatek: add connection from RDMA1 to DPI1stu.hsieh@mediatek.com1-0/+8
2018-06-24drm/mediatek: add connection from RDMA0 to DSI3stu.hsieh@mediatek.com1-0/+4
2018-06-24drm/mediatek: add connection from RDMA0 to DSI2stu.hsieh@mediatek.com1-0/+4
2018-06-24drm/mediatek: add connection from RDMA0 to DPI0stu.hsieh@mediatek.com1-0/+5
2018-06-24drm/mediatek: Update the definition of connection from RDMA1 to DPI0stu.hsieh@mediatek.com1-4/+4
2018-06-24drm/mediatek: add connection from OD1 to RDMA1stu.hsieh@mediatek.com1-0/+4
2018-06-24drm/mediatek: add ddp component OD1stu.hsieh@mediatek.com1-2/+2
2018-06-24drm/mediatek: add ddp component AAL1stu.hsieh@mediatek.com1-1/+1
2018-06-24drm/mediatek: support maximum 64 mutex modstu.hsieh@mediatek.com1-28/+47
2017-04-08drm/mediatek: add support for Mediatek SoC MT2701yt.shen@mediatek.com1-0/+17
2017-04-08drm/mediatek: update display module connectionsyt.shen@mediatek.com1-0/+25
2017-04-08drm/mediatek: add shadow register supportyt.shen@mediatek.com1-0/+25
2017-04-08drm/mediatek: add *driver_data for different hardware settingsyt.shen@mediatek.com1-34/+37
2016-05-06drm/mediatek: Add DRM Driver for Mediatek SoC MT8173.CK Hu1-0/+353
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