summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/intel_pm.c
AgeCommit message (Expand)AuthorFilesLines
2015-07-22drm: Simplify drm_for_each_legacy_plane argumentsDaniel Vetter1-1/+1
2015-07-17drm/i915: Fix divide by zero on watermark updateMika Kuoppala1-1/+3
2015-07-15drm/i915/gen9: Add WaFlushCoherentL3CacheLinesAtContextSwitch workaroundArun Siluvery1-0/+3
2015-07-15drm/i915/gen9: Implement WaDisableKillLogic for gen 9Nick Hoath1-0/+4
2015-07-14drm/i915: Add HAS_CORE_RING_FREQ macroAkash Goel1-1/+1
2015-07-14drm/i915/skl: Restrict the ring frequency table programming to SKLAkash Goel1-1/+2
2015-07-13drm/i915: Update PM interrupts before updating the freqDeepak S1-2/+2
2015-07-13drm/i915/skl: Ring frequency table programming changesAkash Goel1-4/+19
2015-07-13drm/i915/skl: Retrieve the Rpe value from PcodeAkash Goel1-8/+11
2015-07-08drm/i915: use dev_priv for the FBC functionsPaulo Zanoni1-1/+3
2015-07-07drm/i915: s/mdelay/msleep/Daniel Vetter1-3/+3
2015-06-29drm/i915: Zero unused WM1 watermarks on VLV/CHVVille Syrjälä1-0/+6
2015-06-29drm/i915: Don't do PM5/DDR DVFS with multiple pipesVille Syrjälä1-0/+3
2015-06-29drm/i915: Try to make sure cxsr is disabled around plane enable/disableVille Syrjälä1-7/+4
2015-06-29drm/i915: Use the memory latency based WM computation on VLV tooVille Syrjälä1-218/+5
2015-06-29drm/i915: Compute display FIFO split dynamically for CHVVille Syrjälä1-10/+165
2015-06-29drm/i915: CHV DDR DVFS support and another watermark rewriteVille Syrjälä1-6/+312
2015-06-29drm/i915: Read wm values from hardware at init on CHVVille Syrjälä1-0/+141
2015-06-29drm/i915: POSTING_READ() in intel_set_memory_cxsr()Ville Syrjälä1-0/+5
2015-06-26drm/i915: Update rps frequencies for BXTBob Paauwe1-4/+12
2015-06-15drm/i915: Remove more ilk rc6 remnantsDaniel Vetter1-10/+2
2015-06-12drm/i915: Don't enable IPS when pixel rate exceeds 95%Ville Syrjälä1-9/+8
2015-06-12drm/i915: Use cached cdclk valueVille Syrjälä1-1/+1
2015-06-04Merge tag 'v4.1-rc6' into drm-nextDave Airlie1-13/+11
2015-05-28drm/i915: s/dpio_lock/sb_lock/Ville Syrjälä1-2/+2
2015-05-28drm/i915: Kill intel_flush_primary_plane()Ville Syrjälä1-2/+4
2015-05-26drm/i915: Use spinlocks for checking when to waitboostChris Wilson1-11/+20
2015-05-22drm/i915: Introduce DRM_I915_THROTTLE_JIFFIESChris Wilson1-1/+1
2015-05-22drm/i915: Enable GTT caching on gen8Ville Syrjälä1-0/+13
2015-05-22drm/i915: Move WaProgramL3SqcReg1Default:bdw to init_clock_gating()Ville Syrjälä1-0/+10
2015-05-22drm/i915: Use ilk_init_lp_watermarks() on BDWVille Syrjälä1-3/+1
2015-05-21drm/i915: Free RPS boosts for all laggardsChris Wilson1-4/+16
2015-05-21drm/i915: Convert RPS tracking to a intel_rps_client structChris Wilson1-7/+7
2015-05-21drm/i915: Limit mmio flip RPS boostsChris Wilson1-0/+1
2015-05-21drm/i915: Limit ring synchronisation (sw sempahores) RPS boostsChris Wilson1-0/+1
2015-05-21drm/i915: s/\<rq\>/req/gDaniel Vetter1-8/+8
2015-05-20drm/i915/chv: Set min freq to efficient frequency on chvDeepak S1-19/+2
2015-05-20drm/i915/chv: Extend set idle rps wa to chvDeepak S1-7/+0
2015-05-20drm/i915/vlv: Remove wait for for punit to updates freq.Deepak S1-30/+11
2015-05-20drm/i915: Be optimistic about future display engines having 7 WM levelsDamien Lespiau1-1/+1
2015-05-20drm/i915: Adding dbuf support for skl nv12 format.Chandra Konduru1-12/+67
2015-05-19drm/i915: fix screen flickeringThomas Gummerer1-13/+11
2015-05-08drm/i915/skl: Fix WaDisableChickenBitTSGBarrierAckForFFSliceCSDamien Lespiau1-2/+1
2015-05-08drm/i915: s/9/intel_freq_opcode(450)/Ville Syrjälä1-2/+2
2015-05-08drm/i915: Setup static bias for GPUDeepak S1-0/+12
2015-04-16drm/i915: Re-adjusting rc6 promotional timer for chvDeepak S1-2/+2
2015-04-14Merge branch 'topic/bxt-stage1' into drm-intel-next-queuedDaniel Vetter1-2/+31
2015-04-14drm/i915/bxt: add workaround to avoid PTE corruptionRobert Beckett1-0/+2
2015-04-14drm/i915/bxt: add GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ workaroundBen Widawsky1-1/+3
2015-04-14drm/i915/bxt: add GEN8_SDEUNIT_CLOCK_GATE_DISABLE workaroundImre Deak1-0/+11
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-01 00:59:17 +0000