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path: root/drivers/gpu/drm/i915/intel_color.c
AgeCommit message (Expand)AuthorFilesLines
2019-04-29drm/i915: Fix ICL output CSC programmingVille Syrjälä1-3/+3
2019-04-08drm/i915: extract intel_color.h from intel_drv.hJani Nikula1-0/+1
2019-04-03drm/i915: Expose full 1024 LUT entries on ivb+Ville Syrjälä1-42/+33
2019-04-03drm/i915: Add "10.6" LUT mode for i965+Ville Syrjälä1-1/+61
2019-04-03drm/i915: Add 10bit LUT for ilk/snbVille Syrjälä1-10/+39
2019-04-03drm/i915: Implement split/10bit gamma for ivb/hswVille Syrjälä1-21/+92
2019-04-03drm/i915: Don't use split gamma when we don't have toVille Syrjälä1-95/+90
2019-04-03drm/i915: Extract ilk_lut_10()Ville Syrjälä1-16/+11
2019-03-29drm/i915: Program EXT2 GC MAX registersUma Shankar1-0/+22
2019-03-29drm/i915: Fix GCMAX color register programmingUma Shankar1-11/+11
2019-03-28drm/i915: Skip the linear degamma LUT load on ICL+Ville Syrjälä1-27/+64
2019-03-28drm/i915: Drop the pointless linear legacy LUT load on CHVVille Syrjälä1-16/+1
2019-03-28drm/i915: Extract ilk_color_check()Ville Syrjälä1-43/+33
2019-03-28drm/i915: Extract bdw_color_check()Ville Syrjälä1-0/+39
2019-03-28drm/i915: Extract glk_color_check()Ville Syrjälä1-0/+40
2019-03-28drm/i915: Extract icl_color_check()Ville Syrjälä1-17/+53
2019-03-28drm/i915: Extract chv_color_check()Ville Syrjälä1-4/+36
2019-03-28drm/i915: Extract i9xx_color_check()Ville Syrjälä1-5/+28
2019-03-28drm/i915: Turn intel_color_check() into a vfuncVille Syrjälä1-10/+20
2019-03-28drm/i915: Extract check_luts()Ville Syrjälä1-28/+40
2019-03-18drm/i915: Fix legacy gamma mode for ICLVille Syrjälä1-0/+3
2019-03-15drm/i915: Split ilk vs. icl csc matrix handlingVille Syrjälä1-29/+42
2019-03-15drm/i915: Clean the csc limited range/identity programmingVille Syrjälä1-26/+27
2019-03-15drm/i915: Extract ilk_csc_convert_ctm()Ville Syrjälä1-44/+53
2019-03-15drm/i915: Clean up ilk/icl pipe/output CSC programmingVille Syrjälä1-86/+82
2019-03-15drm/i915: Extract ilk_csc_limited_range()Ville Syrjälä1-8/+14
2019-03-15drm/i915: Precompute/readout/check CHV CGM modeVille Syrjälä1-7/+21
2019-03-15drm/i915: Readout and check csc_modeVille Syrjälä1-2/+2
2019-03-13drm/i915/gen11+: First assume next platforms will inherit stuffRodrigo Vivi1-1/+1
2019-02-13drm/i915/icl: Enable pipe output cscUma Shankar1-19/+58
2019-02-13drm/i915/icl: Enable ICL Pipe CSC blockUma Shankar1-1/+4
2019-02-13drm/i915/icl: Add icl pipe degamma and gamma supportUma Shankar1-2/+19
2019-02-13drm/i915/glk: Fix degamma lut programmingUma Shankar1-28/+34
2019-02-08drm/i915: Update DSPCNTR gamma/csc bits during crtc_enable()Ville Syrjälä1-0/+4
2019-02-08drm/i915: Disable pipe gamma when C8 pixel format is usedVille Syrjälä1-1/+7
2019-02-08drm/i915: Turn off pipe CSC when it's not neededVille Syrjälä1-2/+8
2019-02-08drm/i915: Turn off pipe gamma when it's not neededVille Syrjälä1-2/+53
2019-02-08drm/i915: Track pipe csc enable in crtc stateVille Syrjälä1-1/+6
2019-02-08drm/i915: Track pipe gamma enable/disable in crtc stateVille Syrjälä1-1/+27
2019-02-08drm/i915: Populate gamma_mode for all platformsVille Syrjälä1-15/+45
2019-02-07drm/i915: Move LUT programming to happen after vblank waitsVille Syrjälä1-24/+1
2019-02-07drm/i915: Split color mgmt based on single vs. double buffered registersVille Syrjälä1-26/+23
2019-02-07drm/i915: Pull GAMMA_MODE write out from haswell_load_luts()Ville Syrjälä1-16/+20
2019-02-07drm/i915: Constify the state arguments to the color management stuffVille Syrjälä1-64/+76
2019-02-07drm/i915: Precompute gamma_modeVille Syrjälä1-9/+12
2019-02-05drm/i915: Rename HAS_GMCHRodrigo Vivi1-3/+3
2019-01-30drm/i915: Apply LUT validation checks to platforms more accurately (v3)Matt Roper1-30/+30
2019-01-23drm/i915: Validate userspace-provided color management LUT's (v4)Matt Roper1-0/+16
2019-01-21drm/i915/color: switch to kernel typesJani Nikula1-20/+20
2018-12-13drm/i915: Fix Cherryview oops on bootChris Wilson1-3/+6
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