summaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/i915/i915_drv.h
AgeCommit message (Expand)AuthorFilesLines
2020-05-20Merge tag 'drm-intel-next-2020-05-15' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-8/+29
2020-05-15drm/i915: Update DRIVER_DATE to 20200515Joonas Lahtinen1-2/+2
2020-05-14drm/i915: Extract i915_cs_timestamp_{ns_to_ticks,tick_to_ns}()Ville Syrjälä1-0/+12
2020-05-14drm/i915/psr: Use new DP VSC SDP compute routine on PSRGwan-gyeong Mun1-0/+1
2020-05-14Merge tag 'drm-intel-next-2020-04-30' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-2/+2
2020-05-13drm/i915: Drop I915_RESET_TIMEOUT and friendsChris Wilson1-7/+0
2020-05-12drm/i915/ehl: Restrict w/a 1607087056 for EHL/JSLSwathi Dhanavanthri1-0/+5
2020-05-11drm/i915: Stash hpd status bits under dev_privVille Syrjälä1-0/+2
2020-05-09drm/i915: Replace the hardcoded I915_FENCE_TIMEOUTChris Wilson1-1/+9
2020-04-30drm/i915: Update DRIVER_DATE to 20200430Joonas Lahtinen1-2/+2
2020-04-22Merge tag 'drm-misc-next-2020-04-14' of git://anongit.freedesktop.org/drm/drm...Dave Airlie1-0/+3
2020-04-17drm/i915: Update DRIVER_DATE to 20200417Joonas Lahtinen1-2/+2
2020-04-15drm/i915/tgl: Add Wa_14010477008:tglMatt Roper1-0/+2
2020-04-03drm/i915: Store cpu_transcoder_mask in device infoVille Syrjälä1-1/+1
2020-04-02drm/i915/gem: Drop cached obj->bind_countChris Wilson1-0/+1
2020-03-26drm/i915: Use drmm_add_final_kfreeDaniel Vetter1-0/+3
2020-03-26drm/i915: Drop final few uses of drm_i915_private.engineChris Wilson1-1/+0
2020-03-24drm/i915/display/fbc: Make fences a nice-to-have for GEN9+José Roberto de Souza1-0/+1
2020-03-16drm/i915: Remove manual save/resume of fence register stateChris Wilson1-1/+0
2020-03-16drm/i915: Move GGTT fence registers under gt/Chris Wilson1-1/+0
2020-03-13drm/i915: Update DRIVER_DATE to 20200313Rodrigo Vivi1-2/+2
2020-03-06drm/i915/hotplug: Use phy to get the hpd_pin instead of the port (v5)Vivek Kasireddy1-0/+7
2020-03-06drm/i915/gem: Limit struct_mutex to eb_reserveChris Wilson1-6/+0
2020-03-03drm/i915/gvt: only include intel_gvt.h where neededJani Nikula1-2/+0
2020-03-03drm/i915/gvt: make intel_gvt_active internal to intel_gvtJani Nikula1-5/+0
2020-03-03drm/i915/vgpu: improve vgpu abstractionsJani Nikula1-5/+0
2020-03-03drm/i915: move watermark structs more towards usageJani Nikula1-40/+0
2020-03-02drm/i915: Unify the DPLL ref clock frequency trackingImre Deak1-0/+5
2020-03-02drm/i915: Keep the global DPLL state in a DPLL specific structImre Deak1-10/+12
2020-03-02drm/i915: remove unused orig_clock i915 memberJani Nikula1-2/+0
2020-03-02drm/i915: add i915_ioc32.h for compatJani Nikula1-5/+0
2020-03-02drm/i915/dram: hide the dram structs betterJani Nikula1-10/+0
2020-03-02drm/i915/crc: move pipe_crc from drm_i915_private to intel_crtcJani Nikula1-30/+0
2020-02-28drm/i915: Add glk to intel_detect_preproduction_hw()Ville Syrjälä1-0/+2
2020-02-25drm/i915: Update DRIVER_DATE to 20200225Rodrigo Vivi1-2/+2
2020-02-24drm/i915: Update DRIVER_DATE to 20200224Rodrigo Vivi1-1/+1
2020-02-24drm/i915: Update DRIVER_DATE to 20200224Rodrigo Vivi1-2/+2
2020-02-24drm/i915/psr: Force PSR probe only after full initializationJosé Roberto de Souza1-1/+1
2020-02-20drm/i915/guc: Apply new uC status tracking to GuC submission as wellDaniele Ceraolo Spurio1-6/+0
2020-02-20drm/i915/guc: Kill USES_GUC_SUBMISSION macroDaniele Ceraolo Spurio1-3/+0
2020-02-20drm/i915/guc: Kill USES_GUC macroDaniele Ceraolo Spurio1-1/+0
2020-02-19drm/i915: Read rawclk_freq earlierChris Wilson1-1/+0
2020-02-17drm/i915: split out vlv/chv specific suspend/resume codeJani Nikula1-2/+0
2020-02-10drm/i915/dc3co: Add description of how it worksJosé Roberto de Souza1-1/+1
2020-02-05drm/i915: Manipulate DBuf slices properlyStanislav Lisovskiy1-1/+1
2020-02-05drm/i915: Remove skl_ddl_allocation structStanislav Lisovskiy1-9/+2
2020-01-31drm/i915/guc: Introduce guc_is_readyMichal Wajdeczko1-1/+1
2020-01-31drm/i915: Convert cdclk to global stateVille Syrjälä1-38/+7
2020-01-31drm/i915: Convert bandwidth state to global stateVille Syrjälä1-1/+1
2020-01-31drm/i915: Introduce better global state handlingVille Syrjälä1-0/+3