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path: root/drivers/gpu/drm/amd/include
AgeCommit message (Expand)AuthorFilesLines
2019-11-22drm/amdgpu: refine query function of mmhub EDC counter in vg20Dennis Li4-310/+138
2019-11-19drm/amdgpu: add JPEG PG and CG interfaceLeo Liu1-0/+2
2019-11-19drm/amdgpu: add JPEG IP block typeLeo Liu1-1/+2
2019-11-06drm/amd/powerplay: support xgmi pstate setting on powerplay routine V2Evan Quan1-0/+4
2019-10-25drm/amdgpu: Add DC feature mask to disable fractional pwmLeo Li1-0/+1
2019-10-25drm/amdgpu/display: add dc feature mask for psr enablementRoman Li1-0/+1
2019-10-25drm/amdgpu: add VCN0 and VCN1 needed headersJane Jian1-0/+12
2019-10-17drm/amdgpu: update atomfirmware header with memory training related members(v3)Tianci.Yin1-6/+21
2019-10-17drm/amd/display: Add DCN_BASE regsBhawanpreet Lakha1-0/+34
2019-10-17drm/amd/display: Add DP_DPHY_INTERNAL_CTR regsBhawanpreet Lakha1-0/+10
2019-10-15drm/amdgpu: add new SMU 7.1.3 registers for BACOAlex Deucher2-0/+3
2019-10-15drm/amdgpu: add new SMU 7.1.2 registers for BACOAlex Deucher2-0/+3
2019-10-15drm/amdgpu: add new SMU 7.0.1 registers for BACOAlex Deucher2-0/+3
2019-10-15drm/amdgpu: add new BIF 5.0 register for BACOAlex Deucher2-0/+3
2019-10-15drm/amdgpu: add new BIF 4.1 register for BACOAlex Deucher2-0/+3
2019-10-15drm/amd/include: add register define for VML2 and ATCL2Dennis Li2-4/+32
2019-10-15drm/amdgpu/discovery: reserve discovery data at the top of VRAMXiaojie Yuan1-1/+0
2019-10-15drm/amd/powerplay: enable df cstate control on powerplay routineEvan Quan1-0/+6
2019-10-03drm/amd/amdgpu: add IH cg support on soc15 projectKenneth Feng1-0/+4
2019-10-03drm/amdkfd: Eliminate get_atc_vmid_pasid_mapping_validYong Zhao1-5/+3
2019-10-03drm/amdgpu: Add SMUIO values for other I2C controller v2Kent Russell2-0/+268
2019-10-03drm/amdkfd: Fix NULL pointer dereference for set_scratch_backing_va()Yong Zhao1-0/+5
2019-09-16drm/amdgpu: add pcie bif ras related registersGuchun Chen2-0/+55
2019-09-13drm/amd/display: update renoir_ip_offset.hAaron Liu1-1/+1
2019-09-13drm/amdgpu: Support new arcturus mtypeOak Zeng1-0/+1
2019-09-13drm/amdgpu: update nbio v7_4 ip header filesHawking Zhang2-5/+5
2019-09-13drm/amdgpu: add nbif v7_4 irq source header for vega20Hawking Zhang1-0/+42
2019-08-30drm/amdgpu: update IH_CHICKEN in oss 4.0 IP header for VG/RV seriesAaron Liu1-0/+4
2019-08-29drm/amd/display: Add Renoir registers (v3)Bhawanpreet Lakha7-0/+75988
2019-08-27drm/amd/powerplay: Add interface to lock SMU HW I2C.Andrey Grodzovsky1-0/+1
2019-08-27drm/amd: Import smuio_11_0 headers for EEPROM access on Vega20Andrey Grodzovsky2-0/+323
2019-08-23drm/amdgpu/display: add flag for multi-display mclk switchingAlex Deucher1-0/+1
2019-08-21drm/amdgpu: Fix a typo in the include header guard of 'navi12_ip_offset.h'Christophe JAILLET1-2/+2
2019-08-15drm/amd/poweplay: Add amd_pm_funcs callback for mode 2Andrey Grodzovsky1-0/+1
2019-08-15drm/amdgpu: implement querying ras error count for mmhubTao Zhou2-0/+243
2019-08-12drm/amdgpu: add renoir header files (v2)Huang Rui2-0/+1202
2019-08-02drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc headerXiaojie Yuan2-0/+41
2019-08-02drm/amdgpu: add ip offset header for navi12 (v2)Xiaojie Yuan1-0/+1119
2019-08-02drm/amdkfd: Extend CU mask to 8 SEs (v3)Jay Cornwall1-4/+4
2019-08-02drm/amdgpu: Update NBIO headers to add TXCLK3/4Kent Russell2-0/+36
2019-07-31drm/amd/include: add define of TCP_EDC_CNT_NEWDennis Li1-0/+2
2019-07-31drm/amd/include: add bitfield define for EDC registersDennis Li1-0/+157
2019-07-31drm/amdgpu: add umc v6_1_1 IP headersHawking Zhang2-0/+122
2019-07-31drm/amdgpu: add rsmu v_0_0_2 ip headersHawking Zhang2-0/+59
2019-07-30drm/amd/powerplay: add new sensor type for VCN powergate statusEvan Quan1-0/+1
2019-07-30drm/amd/include: adjust base offset of SMUIO and THM for ArcturusLe Ma1-6/+2
2019-07-30drm/amd/powerplay: add smcdpminfo table v4_6 supportEvan Quan1-0/+86
2019-07-30drm/amdgpu/powerplay: add a new interface to set the mp1 stateAlex Deucher1-0/+8
2019-07-18drm/amdgpu: exposing fica registers to df offsetsJonathan Kim1-0/+4
2019-07-18drm/amd/powerplay: correct SW SMU valid mapping checkEvan Quan1-0/+1
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