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path: root/drivers/gpu/drm/amd/display/dc/core
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2019-10-30dc.c:use kzalloc without testzhongshiqi1-0/+4
dc.c:583:null check is needed after using kzalloc function Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: zhongshiqi <zhong.shiqi@zte.com.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-30drm/amd/display: setting the DIG_MODE to the correct value.Zhan liu1-0/+9
[Why] This patch is for fixing Navi14 HDMI display pink screen issue. [How] Call stream->link->link_enc->funcs->setup twice. This is setting the DIG_MODE to the correct value after having been overridden by the call to transmitter control. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-30drm/amd/display: Passive DP->HDMI dongle detection fixMichael Strauss1-6/+18
[WHY] i2c_read is called to differentiate passive DP->HDMI and DP->DVI-D dongles The call is expected to fail in DVI-D case but pass in HDMI case Some HDMI dongles have a chance to fail as well, causing misdetection as DVI-D [HOW] Retry i2c_read to ensure failed result is valid Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-10-30drm/amd/display: do not synchronize "drr" displaysJun Lei1-0/+6
[why] A display that supports DRR can never really be considered "synchronized" with any other display because we can dynamically enable DRR (i.e. without modeset). this will cause their relative CRTC positions to drift and lose sync. this will disrupt features such as MCLK switching that assume and depend on their permanent alignment (that can only change with modeset) [how] check for ignore_msa in stream when considered synchronizability this ignore_msa is basically actually implemented as "supports drr" Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-29drm/amd/display: call update_bw_bounding_boxBhawanpreet Lakha1-0/+5
call update_bw_bounding_box in DC construct Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-29drm/amd/display: Handle Renoir in DCBhawanpreet Lakha1-0/+12
add Renoir DCN version in DC and handle it Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amd/display: flicking observed while installing driver on Navi10 CFhersen wu1-0/+1
[WHY] value of dchub_ref_clock is decided by dchubbub global timer settings which is programmed by vbios command table disp_init. for multi-GPU case, vbios is posted only for primary GPU. without vbios posted for the secondary GPU, value of dchub_ref_clock is not set properly. this value will affect dcn bandwidth calcuation and cause underflow. user will see screen flicking during driver installation for dual GPU case. [HOW] dc init_hw always call vbios command table disp_init to make sure dchubbub global timer is configured and enable. Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amd/display: Expose OTG_V_TOTAL_MID for HW DiagsBayan Zabihiyan1-1/+3
[Why] Existing HW Features, HW Diags test requested that the registers be exposed. [How] Add V_TOTAL_MID to existing DC structures. Make sure values are passed down throughout DC Add Register definition. Program the additional registers Add additional Logic for V_TOTAL_CONTROL. Signed-off-by: Bayan Zabihiyan <bayan.zabihiyan@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amd/display: fix odm stream releaseDmytro Laktyushkin1-33/+32
Need to memset all odm pipes when calling dc_remove_stream_from_ctx Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amd/display: fix dcn20 odm dpp programmingDmytro Laktyushkin1-0/+1
dcn20 requires special casing for odm. This change treats odm as alternative to mpc tree on dcn20. This is planned to be fixed in a future refactor Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amd/display: fix odm pipe copyDmytro Laktyushkin2-1/+7
ODM next and prev pipe were missing from dc_copy_state Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amd/display: support spdifCharlene Liu1-9/+8
[Description] port spdif fix to staging: spdif hardwired to afmt inst 1. spdif func pointer spdif resource allocation (reserve last audio endpoint for spdif only) Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amd/display: refactor Device ID for external chipsQingqing Zhuo2-6/+17
IEEE OUI will now be used while referring to certain vendors. instead of normal index Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amd/display: fix audio endpoint not getting disabled issueSu Sung Chung3-4/+10
[Why] Disable_audio_stream gets enum option as a paramenter which will decide if we free acquired resources or not. However checks for the option is guarded by the other condition which check if audio stream is getting diabled more than once. With both conditions combined, if we attempt to disable audio stream twice in a row, first with keep and second with free as an option, we will never free any resources, which will make system think there is audio endpoint connected even after we plug out the device [How] Get rid of option as parameter to disable_audio_stream and move the part of the code that free acquired resources to outside where to keep or to free resources is actually determined Signed-off-by: Su Sung Chung <Su.Chung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amd/display: re structure odm to allow 4 to 1 supportDmytro Laktyushkin4-134/+95
Currently odm is handled using top_bottom pipe by special casing the differing opps to differentiate from mpc combine. Since top/bottom pipe list was made to track mpc muxing this creates difficulties in adding a 4 pipe odm case support. Rather than continue using mpc combine list, this change reworks odm to use it's own linked list to keep track of odm combine pipes. This also opens up options for using mpo with odm, if a practical use case is ever found. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22Revert "drm/amd/display: Fix underscan not using proper scaling"David Francis1-11/+1
This reverts commit 80e80ec817f161560b4159608fb41bd289abede3. This commit fixed an issue with underscan commits not updating all needed timing values, but through various refactors it is no longer necessary. It causes corruption on odm combine by overwriting the halved h_active in the stream timing Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/display: remove duplicated include from dc_link.cYueHaibing1-4/+0
Remove duplicated include. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/display: Fix 32-bit divide error in wait_for_alt_modeNathan Chancellor1-2/+2
When building arm32 allyesconfig: ld.lld: error: undefined symbol: __aeabi_uldivmod >>> referenced by dc_link.c >>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a >>> referenced by dc_link.c >>> gpu/drm/amd/display/dc/core/dc_link.o:(wait_for_alt_mode) in archive drivers/built-in.a time_taken_in_ns is of type unsigned long long so we need to use div_u64 to avoid this error. Fixes: b5b1f4554904 ("drm/amd/display: Enable type C hotplug") Reported-by: Randy Dunlap <rdunlap@infradead.org> Acked-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: Enable MPO with pre-blend color processing (RGB)Michael Strauss1-0/+2
[Why] DCN10 performs color processing before MPC combination, causes color shift in RGB colorspaces when positive brightness offset is applied However, YCbCr is still unfixed and remains disabled [How] Add layerIndex to dc_plane_state and dc_plane_info structs Re-enable MPO when brightness is adjusted and colorspace is not YCbCr Set rear plane's brightness offset to 0 when front plane visible Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: check hpd before retry verify link capWenjing Liu2-21/+33
[why] During detection link training if a display is disconnected, the current code will retry 3 times of link training on disconnected link before giving up. [how] Before each retry check for HPD status, only retry verify link cap when HPD is still high. Also put a 10ms delay between each retry to improve the chance of success. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: Add and refine DSC logs in enable sequenceNikola Cornij1-8/+26
[why] Some logs messages were not precise and some new log messages were needed after "get packed PPS" function was introduced Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: reprogram VM config when system resumeLewis Huang1-0/+8
[Why] The vm config will be clear to 0 when system enter S4. It will cause hubbub didn't know how to fetch data when system resume. The flip always pending because earliest_inuse_address and request_address are different. [How] Reprogram VM config when system resume Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: Enable type C hotplugEric Yang1-0/+59
[Why and How] We want to change where timing is done for alt mode. Some of the commented out #ifs are needed for DCN20 so we enable them for that case. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: Set DSC before DIG front-end is connected to its back-endNikola Cornij2-24/+74
[why] At the time DIG FE is connected to its BE, the clocks in OTG are enabled and PHY will also be set up. When DSC has to be used to fit the stream into the available bandwidth, without DSC being set DIG could get exposed to the higer bandwidth it (or link) could handle. This causes the HW to "reject" video enable setup (the register shows that video enable was attempted, but the status bit shows it as disabled). [how] - Separate DSC setup into DSC register config and DSC PPS SDP setup - Move most of the DSC setup (register config) to before dcn10_link_encoder_connect_dig_be_to_fe() is called - Set up DSC PPS SDP after DIG FE is connected to its BE. This is because setting DSC PPS SDP before that has no effect. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: enabling seamless boot sequence for dcn2Martin Leung3-22/+56
[Why] Seamless boot (building SW state inheriting BIOS-initialized timing) was enabled on DCN2, including fixes [How] Includes fixes for MPC, DPPCLK, and DIG FE mapping/OTG source select/ Pixel clock. This is part 2 of 2 for seamless boot NV10 Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: fixup DPP programming sequenceJun Lei1-0/+3
[why] DC does not correct account for the fact that DPP DTO is double buffered while DPP ref is not. This means that when DPP ref clock is lowered when it's "safe to lower", the DPP blocks that need an increased divider will temporarily have actual DPP clock drop below minimum while DTO double buffering takes effect. This results in temporary underflow. [how] To fix this, DPP clock cannot be programmed atomically, but rather be broken up into the DTO and the ref. Each has a separate "safe to lower" logic. When doing "prepare" the ref and dividers may only increase. When doing "optimize", both may decrease. It is guaranteed that we won't exceed max DPP clock because we do not use dividers larger than 1. Signed-off-by: Jun Lei <Jun.Lei@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: make firmware info only load once during dc_bios createDmytro Laktyushkin1-5/+2
Currently every time DC wants to access firmware info we make a call into VBIOS. This makes no sense as there is nothing that can change runtime inside fw info and can cause issues when calling unstable bios during bringup. This change eliminate this behavior by only calling bios once for fw info and keeping it stored as part of dc_bios. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-15drm/amd/display: Synchronous DisplayPort Link TrainingDavid Galiffi3-123/+266
[WHY] We require a method to perform synchronous link training. [HOW] Sync LT is broken into 3 basic steps. "Begin" starts the state machine, and resets "preferred" link settings. "Attempt" will attempt to train the link with a given set of training parameters. "End" stops the state machine, and will optionally disable the link phy. Between "Begin" and "End" DPCD:600h must not be set to "2" (D3:Powered Down). Between "Begin" and "End", there may be multiple "Attempts" with different training parameters. Signed-off-by: David Galiffi <david.galiffi@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-12drm/amd/display: use kvmalloc for dc_state (v2)Alex Deucher1-5/+6
It's large and doesn't need contiguous memory. Fixes allocation failures in some cases. v2: kvfree the memory. Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/display: fix a missing null check on a failed kzallocColin Ian King1-0/+2
Currently the allocation of config may fail and a null pointer dereference on config can occur. Fix this by added a null check on a failed allocation of config. Addresses-Coverity: ("Dereference null return") Fixes: c2cd9d04ecf0 ("drm/amd/display: Hook up calls to do stereo mux and dig programming to stereo control interface") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: handle active dongle port type is DP++ or DP caseDale Zhao1-10/+20
[Why]: Some active dongles have DP++ port and DP port at the same time. Current code doesn't cover DP++ case and processes as default DVI case, in which audio is disabled. Because of dual mode, DP case is also treat as DVI case for the other port. [How]: According DP 1.4 spec, add DP++ procedure similar with HDMI case. Also add None dongle type for DP case. Signed-off-by: Dale Zhao <dale.zhao@amd.com> Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Add debug entry to destroy disconnected edp linkLewis Huang1-4/+16
Add a flag to dc_debug_options to determine if a disconnected edp link should be destroyed. Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: do not read link setting if edp not connectedEric Yang1-7/+1
[Why] Previously assume eDP sink present if connector present. Do not need to enforce this restriction. Fix issue where driver attempt to read link setting even though no edp connected. {How] Only read link setting after reading connection status. Signed-off-by: Eric Yang <Eric.Yang2@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: drop ASSERT() if eDP panel is not connectedZhan Liu1-2/+0
[Why] For boards that support eDP but do not have a physical eDP display connected an ASSERT will be thrown. This is not a critical failure and shouldn't be treated as such. [How] Drop the assertion. Signed-off-by: Zhan Liu <zhan.liu@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Clean up dynamic metadata logicJulian Parkin1-17/+10
[Why] Code to enable DCN20 dynamic metadata feature is duplicated in two places and was added to DCE110 enable stream. [How] Create DCN20 specific enable stream function for clarity, and add a hardware sequencer function to program dynamic metadata to avoid the duplicate code. Signed-off-by: Julian Parkin <julian.parkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Only enable audio if speaker allocation existsAlvin Lee1-1/+1
[Why] In dm_helpers_parse_edid_caps, there is a corner case where no speakers can be allocated even though the audio mode count is greater than 0. Enabling audio when no speaker allocations exists can cause issues in the video stream. [How] Add a check to not enable audio unless one or more speaker allocations exist (since doing this can cause issues in the video stream). Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Fix dc_create failure handling and 666 color depthsJulian Parkin2-2/+5
[Why] It is possible (but very unlikely) that constructing dc fails before current_state is created. We support 666 color depth in some scenarios, but this isn't handled in get_norm_pix_clk. It uses exactly the same pixel clock as the 888 case. [How] Check for non null current_state before destructing. Add case for 666 color depth to get_norm_pix_clk to avoid assertion. Signed-off-by: Julian Parkin <julian.parkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: add dcc programming for dual planeDmytro Laktyushkin2-25/+25
Add dual plane dcc programming support for surfaces. Removes unions from plane size and dcc params as they serve no practical purpose only making our code more convoluted. This results in easy dual plane dcc and surface size programming. Temporary diags_dm code is used to handle the interface change without breaking functionality as a diags change needs to be applied after this one. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Implement DAL3 GPU Integer ScalingReza Amini1-0/+16
[WHY] Users want to not have filtering when scaling by integer multiples to native timing. [HOW] If timing is a multiple integer of view, we set number of taps to 1 (effectivly closest neighbour). Signed-off-by: Reza Amini <Reza.Amini@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Tony Cheng <Tony.Cheng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: add set and get clock for testing purposesCharlene Liu1-0/+11
add dc_set_clock add dc_get_clock this is for testing and diagnostics to get/set DPPCLK and DISPCLK. Signed-off-by: Charlene Liu <charlene.liu@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Hook up calls to do stereo mux and dig programming to ↵Murton Liu1-0/+47
stereo control interface [Why] Implementation of stereo mux register is complete, but unused. Need to call functions to write relevant configs. [How] Add function to write stereo config for enable/disable case and call in stereo control interface. Signed-off-by: Murton Liu <murton.liu@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Add MPC 3DLUT resource managementVitaly Prosyak1-2/+1
[Why & How] Number of 3DLUT's in MPC are not equal to number of pipes. Resource management is required. Activate on FPGA entire tm solution which includes the following :hdr multiplier, shaper, 3dlut. Signed-off-by: Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Gary Kattan <Gary.Kattan@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Add debug option to disable timing syncJoshua Aberback1-1/+1
[Why] We want a debug option to disable timing sync for testing. [How] New dc debug option that must be false to call program_timing_sync Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Clear FEC_READY shadow register if DPCD write failsNikola Cornij1-0/+2
[why] As a fail-safe, in case 'set FEC_READY' DPCD write fails, a HW shadow register should be cleared and the internal FEC stat should be set to 'not ready'. This is to make sure HW settings will be consistent with FEC_READY state on the RX. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Chris Park <Chris.Park@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Set FEC_READY always before link trainingNikola Cornij2-12/+20
[why] Right now we FEC_READY is set only before the final link training, i.e. at mode set time. This means FEC_READY won't be set when doing link training as a response to HPD. It also fails UCD400 FEC test in DP compliance. [how] Move FEC_READY setup to link training. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Use helper for determining HDMI signalEric Bernstein1-1/+1
Use helper to determine if HDMI signal when processing avmute. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: use encoder's engine id to find matched free audio deviceTai Man1-1/+7
[Why] On some platforms, the encoder id 3 is not populated. So the encoders are not stored in right order as index (id: 0, 1, 2, 4, 5) at pool. This would cause encoders id 4 & id 5 to fail when finding corresponding audio device, defaulting to the first available audio device. As result, we cannot stream audio into two DP ports with encoders id 4 & id 5. [How] It need to create enough audio device objects (0 - 5) to perform matching. Then use encoder engine id to find matched audio device. Signed-off-by: Tai Man <taiman.wong@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Remove unnecessary NULL check in set_preferred_link_settingsHarry Wentland1-5/+4
[Why] link_stream is never NULL here as we've dereferenced it a couple lines before and have done so for a couple months now. [How] - Drop the NULL check. - Initialize where we know link_stream is non-NULL Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: fix DMCU hang when going into Modern StandbyZi Yu Liao1-1/+8
[why] When the system is going into suspend, set_backlight gets called after the eDP got blanked. Since smooth brightness is enabled, the driver will make a call into the DMCU to ramp the brightness. The DMCU would try to enable ABM to do so. But since the display is blanked, this ends up causing ABM1_ACE_DBUF_REG_UPDATE_PENDING to get stuck at 1, which results in a dead lock in the DMCU firmware. [how] Disable brightness ramping when the eDP display is blanked. Signed-off-by: Zi Yu Liao <ziyu.liao@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Read max down spreadDerek Lai1-0/+7
[Why] When launch D10.2, driver will write DPCD 0x107 with 0x00 [How] Read MAX_DOWNSPREAD (0x0003h) then keep in current link settings Signed-off-by: Derek Lai <Derek.Lai@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-04-26 07:19:02 +0000