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2019-09-26Merge tag 'drm-fixes-5.4-2019-09-25' of ↵drm-next-2019-09-27Dave Airlie1-0/+3
git://people.freedesktop.org/~agd5f/linux into drm-next drm-fixes-5.4-2019-09-25: amdgpu: - Fix a 64 bit divide - Prevent a memory leak in a failure case in dc - Load proper gfx firmware on navi14 variants drm-fixes-5.4-2019-09-19: amdgpu: - Add more navi12 and navi14 PCI ids - Misc fixes for renoir - Fix bandwidth issues with multiple displays on vega20 - Support for Dali - Fix a possible oops with KFD on hawaii - Fix for backlight level after resume on some APUs - Other misc fixes Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190925213500.3490-1-alexander.deucher@amd.com
2019-09-26Merge tag 'drm-misc-next-fixes-2019-09-23' of ↵Dave Airlie1-3/+2
git://anongit.freedesktop.org/drm/drm-misc into drm-next - Multiple panfrost fixes for regulator support and page fault handling - Some cleanups and fixes in the self-refresh helpers - Some cleanups and fixes in the atomic helpers Signed-off-by: Dave Airlie <airlied@redhat.com> From: Maxime Ripard <mripard@kernel.org> Link: https://patchwork.freedesktop.org/patch/msgid/20190923160946.nvaqiw5j7fpcdhc7@gilmour
2019-09-18drm/atomic: Rename crtc_state->pageflip_flags to async_flipDaniel Vetter1-3/+2
It's the only flag anyone actually cares about. Plus if we're unlucky, the atomic ioctl might need a different flag for async flips. So better to abstract this away from the uapi a bit. Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Michel Dänzer <michel@daenzer.net> Cc: Alex Deucher <alexdeucher@gmail.com> Cc: Adam Jackson <ajax@redhat.com> Cc: Sean Paul <sean@poorly.run> Cc: David Airlie <airlied@linux.ie> Signed-off-by: Daniel Vetter <daniel.vetter@intel.com> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Daniel Vetter <daniel@ffwll.ch> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: Leo Li <sunpeng.li@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Cc: David Francis <David.Francis@amd.com> Cc: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Cc: Ben Skeggs <bskeggs@redhat.com> Cc: "Christian König" <christian.koenig@amd.com> Cc: Ilia Mirkin <imirkin@alum.mit.edu> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/msgid/20190903190642.32588-3-daniel.vetter@ffwll.ch
2019-09-17drm/amd/display: Restore backlight brightness after system resumeKai-Heng Feng1-0/+1
Laptops with AMD APU doesn't restore display backlight brightness after system resume. This issue started when DC was introduced. Let's use BL_CORE_SUSPENDRESUME so the backlight core calls update_status callback after system resume to restore the backlight level. Tested on Dell Inspiron 3180 (Stoney Ridge) and Dell Latitude 5495 (Raven Ridge). Cc: <stable@vger.kernel.org> Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-17drm/amdgpu: disable stutter mode for renoirAaron Liu1-0/+2
With stutter mode enabled, NMI prints frequently. Disable stutter for the moment because NMI warning storm, and will enable it back till the issue is addressed Signed-off-by: Aaron Liu <aaron.liu@amd.com> Acked-by: Huang Rui <ray.huang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-09-06Merge tag 'drm-next-5.4-2019-08-30' of ↵Dave Airlie1-1/+15
git://people.freedesktop.org/~agd5f/linux into drm-next drm-next-5.4-2019-08-30: amdgpu: - Add DC support for Renoir - Add some GPUVM hw bug workarounds - add support for the smu11 i2c controller - GPU reset vram lost bug fixes - Navi1x powergating fixes - Navi12 power fixes - Renoir power fixes - Misc bug fixes and cleanups Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190830212650.5055-1-alexander.deucher@amd.com
2019-08-29drm/amd/display: Handle Renoir in amdgpu_dm (v2)Bhawanpreet Lakha1-0/+14
Hook up renoir support to KMS. v2: squash in "Fixes for Renoir in amdgpu_dm" Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-27drm/amd/display: Fix error messageAndrey Grodzovsky1-1/+1
Since reservation_object_wait_timeout_rcu is called with interruptable set to false it's wrong to say 'or interrupted' in the error message. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-27Merge tag 'drm-next-5.4-2019-08-23' of ↵Dave Airlie5-69/+182
git://people.freedesktop.org/~agd5f/linux into drm-next drm-next-5.4-2019-08-23: amdgpu: - Enable power features on Navi12 - Enable power features on Arcturus - RAS updates - Initial Renoir APU support - Enable power featyres on Renoir - DC gamma fixes - DCN2 fixes - GPU reset support for Picasso - Misc cleanups and fixes scheduler: - Possible race fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190823202620.3870-1-alexander.deucher@amd.com
2019-08-23drm/amd/display: MST topology debugfsDavid Francis1-0/+24
DRM provides drm_dp_mst_dump_topology, which prints useful information about MST devices Hook this up to a debugfs file named amdgpu_mst_topology Signed-off-by: David Francis <David.Francis@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-23drm/amdgpu/display: add flag for multi-display mclk switchingAlex Deucher1-0/+3
Add a dcfeaturemask flag for mclk switching. Disable by default; enable once the feature has seen more testing. Set amdgpu.dcfeaturemask=2 on the kernel command line in grub to enable this. Acked-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-22drm/amd/display: Enable SST DSC in DMDavid Francis2-12/+24
In create_stream_for_sink, check for SST DP connectors Parse DSC caps to DC format, then, if DSC is supported, compute the config DSC hardware will be programmed by dc_commit_state Tested-by: Mikita Lipski <Mikita.Lipski@amd.com> Signed-off-by: David Francis <David.Francis@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/display: Lock the CRTC when setting CRC sourceNicholas Kazlauskas1-12/+51
[Why] We need to ensure that we're holding the lock on the CRTC when setting the CRC source since we're modifying the CRTC state directly. We also need to wait for any outstanding non-blocking commits to finish so they aren't reading state that's potentially being modified - non-blocking commits don't hold the CRTC lock while doing commit tail work. [How] Lock the CRTC using its mutex. While holding the lock check if there's any commit active on the CRTC - if there is, it's non-blocking and we should wait until it's finished by waiting for hw_done to be signaled since that's the last point where we touch CRTC state. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/display: Split out DC programming for CRC captureNicholas Kazlauskas3-44/+49
[Why] Calling amdgpu_dm_crtc_set_crc_source in amdgpu_dm directly has the consequence of adding additional vblank references or starting DPRX CRC capture more than once without calling stop first. Vblank references for CRC capture should be managed entirely by opening and closing the CRC file from userspace. Stream state also shouldn't be required on the CRC so we can close the file after the CRTC has been disabled. [How] Do DC programming required for configuring CRC capture separately from setting the source. Whenever we re-enable or reset a CRC this programming should be reapplied. CRC vblank reference handling in amdgpu_dm can be entirely dropped after this. Stream state also no longer needs to be required since we can just defer the programming to when the stream is actually enabled. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/display: Use connector list for finding DPRX CRC auxNicholas Kazlauskas1-4/+15
[Why] This change is a refactor in preparation for adding locking and removing the requirement for a stream state on the CRTC for enabling CRC capture to fix igt@kms_plane_multiple@* warnings. [How] We can get the aux by finding the matching connector for the CRTC with the assumption that we're not doing cloning. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/display: Check return code for CRC drm_crtc_vblank_getNicholas Kazlauskas1-1/+5
[Why] The call to drm_crtc_vblank_get can fail if vblank is disabled and we try to increment the reference. Since drm_crtc_vblank_get internally drops the reference when it fails it means the subsequent drm_crtc_vblank_put(...) when closing the file drops a zero reference. This was found via igt@kms_plane@pixel-format-pipe-A-planes. [How] Check the return code and return it on failure. We wouldn't have been able to enable CRC reading anyway since vblank wasn't enabled. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <David.Francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21drm/amd/display: Calculate bpc based on max_requested_bpcNicholas Kazlauskas1-2/+14
[Why] The only place where state->max_bpc is updated on the connector is at the start of atomic check during drm_atomic_connector_check. It isn't updated when adding the connectors to the atomic state after the fact. It also doesn't necessarily reflect the right value when called in amdgpu during mode validation outside of atomic check. This can cause the wrong bpc to be used even if the max_requested_bpc is the correct value. [How] Don't rely on state->max_bpc reflecting the real bpc value and just do the min(...) based on display info bpc and max_requested_bpc. Fixes: 01933ba42d3d ("drm/amd/display: Use current connector state if NULL when checking bpc") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-21Merge tag 'drm-misc-next-2019-08-19' of ↵Dave Airlie1-1/+1
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.4: UAPI Changes: Cross-subsystem Changes: Core Changes: - dma-buf: add reservation_object_fences helper, relax reservation_object_add_shared_fence, remove reservation_object seq number (and then restored) - dma-fence: Shrinkage of the dma_fence structure, Merge dma_fence_signal and dma_fence_signal_locked, Store the timestamp in struct dma_fence in a union with cb_list Driver Changes: - More dt-bindings YAML conversions - More removal of drmP.h includes - dw-hdmi: Support get_eld and various i2s improvements - gm12u320: Few fixes - meson: Global cleanup - panfrost: Few refactors, Support for GPU heap allocations - sun4i: Support for DDC enable GPIO - New panels: TI nspire, NEC NL8048HL11, LG Philips LB035Q02, Sharp LS037V7DW01, Sony ACX565AKM, Toppoly TD028TTEC1 Toppoly TD043MTEA1 Signed-off-by: Dave Airlie <airlied@redhat.com> [airlied: fixup dma_resv rename fallout] From: Maxime Ripard <maxime.ripard@bootlin.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190819141923.7l2adietcr2pioct@flea
2019-08-15drm/amd/display: Enable MPO with pre-blend color processing (RGB)Michael Strauss1-0/+3
[Why] DCN10 performs color processing before MPC combination, causes color shift in RGB colorspaces when positive brightness offset is applied However, YCbCr is still unfixed and remains disabled [How] Add layerIndex to dc_plane_state and dc_plane_info structs Re-enable MPO when brightness is adjusted and colorspace is not YCbCr Set rear plane's brightness offset to 0 when front plane visible Signed-off-by: Michael Strauss <michael.strauss@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Acked-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-13dma-buf: rename reservation_object to dma_resvChristian König1-1/+1
Be more consistent with the naming of the other DMA-buf objects. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Link: https://patchwork.freedesktop.org/patch/323401/
2019-08-12Merge tag 'drm-next-5.4-2019-08-09' of ↵Dave Airlie5-99/+344
git://people.freedesktop.org/~agd5f/linux into drm-next drm-next-5.4-2019-08-09: Same as drm-next-5.4-2019-08-06, but with the readq/writeq stuff fixed and 5.3-rc3 backmerged. amdgpu: - Add navi14 support - Add navi12 support - Add Arcturus support - Enable mclk DPM for Navi - Misc DC display fixes - Add perfmon support for DF - Add scatter/gather display support for Raven - Improve SMU handling for GPU reset - RAS support for GFX - Drop last of drmP.h - Add support for wiping memory on buffer release - Allow cursor async updates for fb swaps - Misc fixes and cleanups amdkfd: - Add navi14 support - Add navi12 support - Add Arcturus support - CWSR trap handlers updates for gfx9, 10 - Drop last of drmP.h - Update MAINTAINERS radeon: - Misc fixes and cleanups - Make kexec more reliable by tearing down the GPU ttm: - Add release_notify callback uapi: - Add wipe memory on release flag for buffer creation Signed-off-by: Dave Airlie <airlied@redhat.com> [airlied: resolved conflicts with ttm resv moving] From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190809184807.3381-1-alexander.deucher@amd.com
2019-08-06drm/amd/display: Block immediate flips for non-fast updatesNicholas Kazlauskas2-1/+16
[Why] Underflow can occur in the case where we change buffer pitch, DCC state, rotation or mirroring for a plane while also performing an immediate flip. It can also generate a p-state warning stack trace on DCN1 which is typically observed during the cursor handler pipe locking because of how frequent cursor updates can occur. [How] Store the update type on each CRTC - every plane will have access to the CRTC state if it's flipping. If the update type is not UPDATE_TYPE_FAST then the immediate flip should be disallowed. No changes to the target vblank sequencing need to be done, we just need to ensure that the surface registers do a double buffered update. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <david.francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06drm/amd/display: Validate dc_plane_info and dc_plane_size in atomic checkNicholas Kazlauskas1-0/+24
[Why] Pitch, DCC, rotation and mirroring can result in updates that are not UPDATE_TYPE_FAST but UPDATE_TYPE_MED instead. DC needs dc_plane_info and dc_plane_size to make this determination and we aren't currently passing this into DC during atomic check. Underflow (visible or non-visible) can occur if we don't validate this correctly. This also will generally trigger p-state warnings, typically via the cursor handler when locking. [How] Get the framebuffer tiling flags and generate the required structures for DC in dm_determine_update_type_for_commit. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: David Francis <david.francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-06drm/amdgpu: switch driver from bo->resv to bo->base.resvGerd Hoffmann1-1/+1
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Christian König <christian.koenig@amd.com> Link: http://patchwork.freedesktop.org/patch/msgid/20190805140119.7337-14-kraxel@redhat.com
2019-08-02drm/amd/display: Add missing NV12 asic IDsRoman Li1-0/+4
Add missing navi12 asic ids. Signed-off-by: Roman Li <Roman.Li@amd.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amd/display: Don't replace the dc_state for fast updatesNicholas Kazlauskas1-0/+23
[Why] DRM private objects have no hw_done/flip_done fencing mechanism on their own and cannot be used to sequence commits accordingly. When issuing commits that don't touch the same set of hardware resources like page-flips on different CRTCs we can run into the issue below because of this: 1. Client requests non-blocking Commit #1, has a new dc_state #1, state is swapped, commit tail is deferred to work queue 2. Client requests non-blocking Commit #2, has a new dc_state #2, state is swapped, commit tail is deferred to work queue 3. Commit #2 work starts, commit tail finishes, atomic state is cleared, dc_state #1 is freed 4. Commit #1 work starts, commit tail encounters null pointer deref on dc_state #1 In order to change the DC state as in the private object we need to ensure that we wait for all outstanding commits to finish and that any other pending commits must wait for the current one to finish as well. We do this for MEDIUM and FULL updates. But not for FAST updates, nor would we want to since it would cause stuttering from the delays. FAST updates that go through dm_determine_update_type_for_commit always create a new dc_state and lock the DRM private object if there are any changed planes. We need the old state to validate, but we don't actually need the new state here. [How] If the commit isn't a full update then the use after free can be resolved by simply discarding the new state entirely and retaining the existing one instead. With this change the sequence above can be reexamined. Commit #2 will still free Commit #1's reference, but before this happens we actually added an additional reference as part of Commit #2. If an update comes in during this that needs to change the dc_state it will need to wait on Commit #1 and Commit #2 to finish. Then it'll swap the state, finish the work in commit tail and drop the last reference on Commit #2's dc_state. Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204181 Fixes: 004b3938e637 ("drm/amd/display: Check scaling info when determing update type") Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: David Francis <david.francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amd/display: Skip determining update type for async updatesNicholas Kazlauskas1-7/+20
[Why] By passing through the dm_determine_update_type_for_commit for atomic commits that can be done asynchronously we are incurring a performance penalty by locking access to the global private object and holding that access until the end of the programming sequence. This is also allocating a new large dc_state on every access in addition to retaining all the references on each stream and plane until the end of the programming sequence. [How] Shift the determination for async update before validation. Return early if it's going to be an async update. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: David Francis <david.francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amd/display: Allow cursor async updates for framebuffer swapsNicholas Kazlauskas1-10/+0
[Why] We previously allowed framebuffer swaps as async updates for cursor planes but had to disable them due to a bug in DRM with async update handling and incorrect ref counting. The check to block framebuffer swaps has been added to DRM for a while now, so this check is redundant. The real fix that allows this to properly in DRM has also finally been merged and is getting backported into stable branches, so dropping this now seems to be the right time to do so. [How] Drop the redundant check for old_fb != new_fb. With the proper fix in DRM, this should also fix some cursor stuttering issues with xf86-video-amdgpu since it double buffers the cursor. IGT tests that swap framebuffers (-varying-size for example) should also pass again. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: David Francis <david.francis@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amd/display: Use switch table for dc_to_smu_clock_typeLeo Li1-12/+25
Using a static int array will cause errors if the given dm_pp_clk_type is out-of-bounds. For robustness, use a switch table, with a default case to handle all invalid values. v2: 0 is a valid clock type for smu_clk_type. Return SMU_CLK_COUNT instead on invalid mapping. Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-08-02drm/amd/display: Use proper enum conversion functionsNathan Chancellor1-2/+2
clang warns: drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:336:8: warning: implicit conversion from enumeration type 'enum smu_clk_type' to different enumeration type 'enum amd_pp_clock_type' [-Wenum-conversion] dc_to_smu_clock_type(clk_type), ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.c:421:14: warning: implicit conversion from enumeration type 'enum amd_pp_clock_type' to different enumeration type 'enum smu_clk_type' [-Wenum-conversion] dc_to_pp_clock_type(clk_type), ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ There are functions to properly convert between all of these types, use them so there are no longer any warnings. Fixes: a43913ea50a5 ("drm/amd/powerplay: add function get_clock_by_type_with_latency for navi10") Fixes: e5e4e22391c2 ("drm/amd/powerplay: add interface to get clock by type with latency for display (v2)") Link: https://github.com/ClangBuiltLinux/linux/issues/586 Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu/powerplay: provide the interface to disable uclk switch for DALKenneth Feng1-0/+14
provide the interface for DAL to disable uclk switch on navi10. in this case, the uclk will be fixed to maximum. this is a workaround when display configuration causes underflow issue. Signed-off-by: Kenneth Feng <kenneth.feng@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amdgpu: Fix amdgpu_display_supported_domains logic.Andrey Grodzovsky1-1/+1
Add restriction to dissallow GTT domain if the relevant BO doesn't have USWC flag set to avoid the APU hang scenario. Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/display: enable S/G for RAVEN chipShirish S1-1/+1
enables gpu_vm_support in dm and adds AMDGPU_GEM_DOMAIN_GTT as supported domain v2: Move BO placement logic into amdgpu_display_supported_domains v3: Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains. v4: amdgpu_bo_validate_uswc moved to sepperate patch. Signed-off-by: Shirish S <shirish.s@amd.com> Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-30drm/amd/display: Use dev_get_drvdataChuhong Yuan1-2/+1
Instead of using to_pci_dev + pci_get_drvdata, use dev_get_drvdata to make code simpler. Signed-off-by: Chuhong Yuan <hslester96@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-25drm/amd/display: Implement MST Aux device registrationLeo Li1-1/+23
Implement late_register and early_unregister hooks for MST connectors. Call drm helpers for MST connector registration, which registers the AUX devices. Cc: Jerry Zuo <Jerry.Zuo@amd.com> Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190723232808.28128-10-sunpeng.li@amd.com
2019-07-25drm/amd/display: Use connector kdev as aux device parentLeo Li1-1/+1
Set the connector's kernel device as the parent for the aux kernel device. This allows udev rules to access connector attributes when creating symlinks to aux devices. For example, the following udev rule: SUBSYSTEM=="drm_dp_aux_dev", SUBSYSTEMS=="drm", ATTRS{edid}=="*", SYMLINK+="drm_dp_aux/by-name/$id" Will create the following symlinks using the connector's name: $ ls /dev/drm_dp_aux/by-name/ card0-DP-1 card0-DP-2 card0-DP-3 Cc: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190723232808.28128-6-sunpeng.li@amd.com
2019-07-18drm/amd/display: add dcc programming for dual planeDmytro Laktyushkin1-21/+21
Add dual plane dcc programming support for surfaces. Removes unions from plane size and dcc params as they serve no practical purpose only making our code more convoluted. This results in easy dual plane dcc and surface size programming. Temporary diags_dm code is used to handle the interface change without breaking functionality as a diags change needs to be applied after this one. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: add pipe CRC sources without disabling dithering.Dingchen Zhang2-16/+48
[Why] need to verify the impact of spatial dithering on 8bpc bypass mode. [How] added CRC sources and configure dihter option from dc stream. Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com> Reviewed-by: Hanghong Ma <Hanghong.Ma@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: add functionality to get pipe CRC source.Dingchen Zhang3-0/+18
[Why] We need to check the pipe crc source through debugfs for bypass mode test. [How] add implementation of amdgpu_dm_crtc_get_crc_sources and hook into drm_crtc callback get_crc_sources. Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: add functionality to grab DPRX CRC entries.Dingchen Zhang4-44/+136
[Why] We need to compare DPRX CRCs with framebuffer CRCs for digital bypass mode. [How] Hook into DRM to grab DP receiver CRCs through drm_dp_start_crc. Signed-off-by: Dingchen Zhang <dingchen.zhang@amd.com> Reviewed-by: Harry Wentland <Harry.Wentland@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: skip to load dmcu firmware for navi14Xiaojie Yuan1-0/+1
not needed for navi14 at the moment. Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: add nv14 cases to amdgpu_dmBhawanpreet Lakha1-0/+7
Mostly shared with navi10. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-18drm/amd/display: Force uclk to max for every stateNicholas Kazlauskas1-3/+3
Workaround for now to avoid underflow. The uclk switch time should really be bumped up to 404, but doing so would expose p-state hang issues for higher bandwidth display configurations. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-11drm/amdgpu: Print out voltage in DM_PPLIBPaul Menzel1-1/+2
As the clock is already logged, also log the voltage. Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-11drm/amd/display: Add drm_audio_component support to amdgpu_dmNicholas Kazlauskas2-0/+247
[Why] The drm_audio_component can be used to give pin ELD notifications directly to the sound driver. This fixes audio endpoints disappearing due to missing unsolicited notifications. [How] Send the notification via the audio component whenever we enable or disable audio state on a stream. This matches what i915 does with their drm_audio_component and what Takashi Iwai's proposed hack for radeon/amdpgu did. This is a bit delayed in when the notification actually occurs, however. We wait until after all the programming is complete rather than sending the notification mid sequence. Particular care is needed for the get ELD callback since it can happen outside the locking and fencing DRM does for atomic commits. Cc: Leo Li <sunpeng.li@amd.com> Cc: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-07-02drm/amdgpu/display: fix interrupt client id for naviAlex Deucher1-4/+1
All asics newer than vega10 use client ids, so simplify the check. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-25drm/amd/amdgpu: Check stream in amdgpu_dm_commit_planesErnst Sjöstrand1-1/+2
Reported by smatch: amdgpu_dm.c:5637 amdgpu_dm_commit_planes() error: we previously assumed 'acrtc_state->stream' could be null This seems to be checked for null pretty consistently elsewhere. Signed-off-by: Ernst Sjöstrand <ernstp@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-25Merge branch 'drm-next' into drm-next-5.3Alex Deucher8-12/+15
Backmerge drm-next and fix up conflicts due to drmP.h removal. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: Rework CRTC color managementNicholas Kazlauskas3-159/+356
[Why] To prepare for the upcoming DRM plane color management properties we need to correct a lot of wrong behavior and assumptions made for CRTC color management. The documentation added by this commit in amdgpu_dm_color explains how the HW color pipeline works and its limitations with the DRM interface. The current implementation does the following wrong: - Implicit sRGB DGM when no CRTC DGM is set - Implicit sRGB RGM when no CRTC RGM is set - No way to specify a non-linear DGM matrix that produces correct output - No way to specify a correct RGM when a linear DGM is used We had workarounds for passing kms_color tests but not all of the behavior we had wrong was covered by these tests (especially when it comes to non-linear DGM). Testing both DGM and RGM at the same time isn't something kms_color tests well either. [How] The specifics for how color management works in AMDGPU and the new behavior can be found by reading the documentation added to amdgpu_dm_color.c from this patch. All of the incorrect cases from the old implementation have been addressed for the atomic interface, but there still a few TODOs for the legacy one. Note: this does cause regressions for kms_color@pipe-a-ctm-* over HDMI. The result looks correct from visual inspection but the CRC no longer matches. For reference, the test was previously doing the following: linear degamma -> CTM -> sRGB regamma -> RGB to YUV (709) -> ... Now the test is doing: linear degamma -> CTM -> linear regamma -> RGB to YUV (709) -> ... Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Sun peng Li <Sunpeng.Li@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2019-06-22drm/amd/display: update DSC MST DP virtual DPCD peer device enumeration policyWenjing Liu1-0/+14
[why] Current policy assumes virtual DPCD peer device as an individual MST branch device with 1 input and 1 output. However this is only true for virtual DP-to-DP peer device. In general there are three types of virtual DP peer devices. 1. Sink peer device with virtual DPCD. 2. Virtual DP-to-DP Peer device with virtual DPCD. 3. Virtual DP-to-HDMI Protocol Converter Peer Device with Virtual DPCD. So we should break the assumption and handle all three types. [how] DP-to-DP peer device will have virtual DPCD cap upstream. Sink peer device will have virtual DPCD on the logical port. Dp to HDMI protocol converter peer device will have virtual DPCD on its converter port. For DSC capable Synaptics non VGA port we workaround by enumerating a virutal DPCD peer device on its upstream even if it doesn't have one. Signed-off-by: Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-05-11 22:18:46 +0000