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path: root/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
AgeCommit message (Expand)AuthorFilesLines
2020-07-15drm/amdgpu: enable cp_fw_write_wait for navy_flounderJiansong Chen1-0/+1
2020-07-15drm/amdgpu/gfx10: add gc golden setting for navy_flounderJiansong Chen1-0/+48
2020-07-15drm/amdgpu: force pa_sc_tile_steering_override to 0 for navy_flounderJiansong Chen1-1/+2
2020-07-15drm/amdgpu: configure navy_flounder gfx according to gfx 10.3Tao Zhou1-0/+9
2020-07-15drm/amdgpu: add gfx ip block for navy_flounderJiansong Chen1-0/+4
2020-07-15drm/amdgpu/gfx10: add clockgating support for navy_flounderJiansong Chen1-0/+1
2020-07-15drm/amdgpu/gfx10: add support for navy_flounder firmwareJiansong Chen1-0/+10
2020-07-15drm/amdgpu: optimize rlcg write for gfx_v10Jack Zhang1-7/+19
2020-07-10drm/amdgpu/gfx10: fix race condition for kiqJack Xiao1-1/+8
2020-07-10drm/amdgpu: remove unnecessary logic of ASIC checkLikun Gao1-5/+0
2020-07-08drm/amdgpu: use RREG32_KIQ to read register when get cg stateLikun Gao1-5/+5
2020-07-02drm/amdgpu: Clean up KFD VMID assignmentFelix Kuehling1-4/+2
2020-07-01drm/amdgpu/sriov: Need to clear kiq positionEmily Deng1-0/+6
2020-07-01drm/amdgpu: update golden setting for sienna_cichlidLikun Gao1-0/+2
2020-07-01drm/amdgpu: enable gfxoff for sienna_cichlidLikun Gao1-3/+1
2020-07-01drm/amdgpu: only use one gfx pipe for Sienna_CichlidLikun Gao1-2/+2
2020-07-01drm/amdgpu/sriov : Use kiq to do tlb invalidation for gfx10 on sriovshaoyunl1-0/+3
2020-07-01drm/amdgpu: update golden setting for sienna_cichlidLikun Gao1-1/+1
2020-07-01drm/amdgpu: enable 3D pipe 1 on Sienna_CichlidLikun Gao1-1/+13
2020-07-01drm/amdgpu: update golden setting for gfx10.3Likun Gao1-1/+3
2020-07-01drm/amdgpu: drop gfx_v10_0_tiling_mode_table_initHawking Zhang1-8/+0
2020-07-01drm/amdgpu: disable gfxoff for sienna_cichlidLikun Gao1-0/+3
2020-07-01drm/amdgpu: add cp firmware backdoor loading trigerLikun Gao1-0/+37
2020-07-01drm/amdgpu: force pa_sc_tile_steering_override to 0 for gfx10.3Hawking Zhang1-13/+8
2020-07-01drm/amdgpu/gfx10: add gc golden setting for sienna_cichlidLikun Gao1-0/+55
2020-07-01drm/amdgpu: update the num of queue per pipe for mec on sienna_cichlidLikun Gao1-1/+8
2020-06-03drm/amdgpu/gfx10: change register configure for sienna_cichlidLikun Gao1-91/+278
2020-06-03drm/amdgpu: add gfx ip block for sienna_cichlid (v3)Likun Gao1-0/+15
2020-06-03drm/amdgpu/gfx10: add clockgating support for sienna_cichlidLikun Gao1-0/+1
2020-06-03drm/amdgpu/gfx10: add support for sienna_cichlid firmwareLikun Gao1-0/+10
2020-05-28drm/amd/amdgpu: Fix the CGCG setting is overwritten for SRIOV.Gavin Wan1-1/+6
2020-05-28drm/amdgpu/gfx10: add navi12 to gfxoff caseAlex Deucher1-0/+1
2020-05-18drm/amdgpu: apply AMDGPU_IB_FLAG_EMIT_MEM_SYNC to compute IBs too (v3)Marek Olšák1-1/+3
2020-05-18drm/amdgpu: Add mem_sync implementation for all the ASICs.Andrey Grodzovsky1-1/+26
2020-05-14drm/amdgpu: turn back rlcg write for gfx_v10Yintian Tao1-8/+6
2020-05-08drm/amdgpu: implement soft_recovery for gfx10Alex Deucher1-0/+14
2020-05-06drm/amdgpu: drop unnecessary cancel_delayed_work_sync on PG ungateEvan Quan1-5/+1
2020-05-06drm/amdgpu: disable MGCG/MGLS also on gfx CG ungateEvan Quan1-1/+1
2020-05-01amd/amdgpu: Limit rlcg write registers only for nv12shaoyunl1-7/+25
2020-05-01drm/amdgpu: check SMU NULL ptr on gfx hw initLikun Gao1-7/+9
2020-04-28drm/amdgpu: Fix per-IB secure flag GFX hangHuang Rui1-7/+8
2020-04-28drm/amdgpu: Move to a per-IB secure flag (TMZ)Luben Tuikov1-16/+7
2020-04-28drm/amdgpu: implement TMZ accessor (v3)Luben Tuikov1-1/+1
2020-04-28drm/amdgpu: enable TMZ bit in FRAME_CONTROL for gfx10Aaron Liu1-1/+1
2020-04-28drm/amdgpu: expand the context control interface with trust flagHuang Rui1-1/+3
2020-04-28drm/amdgpu: expand the emit tmz interface with trusted flagHuang Rui1-4/+12
2020-04-24drm/amdgpu: skip cg/pg set for SRIOVMonk Liu1-0/+7
2020-04-23drm/amdgpu: request reg_val_offs each kiq read regYintian Tao1-4/+4
2020-04-22drm/amdgpu: change how we update mmRLC_SPM_MC_CNTLChristian König1-3/+10
2020-04-09drm/amd/amdgpu: Correct gfx10's CG sequenceChengming Gui1-8/+15
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