diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index d9a33ca768f3..b44e0c607b1b 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -39,7 +39,10 @@ #include "atom.h" #include "avivod.h" +#include "evergreen.h" +#include "r600.h" #include "r600d.h" +#include "rv770.h" #include "radeon.h" #include "radeon_asic.h" #include "radeon_audio.h" @@ -111,8 +114,6 @@ static void r600_gpu_init(struct radeon_device *rdev); void r600_fini(struct radeon_device *rdev); void r600_irq_disable(struct radeon_device *rdev); static void r600_pcie_gen2_enable(struct radeon_device *rdev); -extern int evergreen_rlc_resume(struct radeon_device *rdev); -extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev); /* * Indirect registers accessor @@ -1080,7 +1081,6 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && !(rdev->flags & RADEON_IS_AGP)) { void __iomem *ptr = (void *)rdev->gart.ptr; - u32 tmp; /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL @@ -1088,7 +1088,7 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev) * method for them. */ WREG32(HDP_DEBUG1, 0); - tmp = readl((void __iomem *)ptr); + readl((void __iomem *)ptr); } else WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); @@ -2954,7 +2954,7 @@ bool r600_semaphore_ring_emit(struct radeon_device *rdev, * @src_offset: src GPU address * @dst_offset: dst GPU address * @num_gpu_pages: number of GPU pages to xfer - * @fence: radeon fence object + * @resv: DMA reservation object to manage fences * * Copy GPU paging using the CP DMA engine (r6xx+). * Used by the radeon ttm implementation to move pages if @@ -4373,7 +4373,7 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev) /** * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO - * rdev: radeon device structure + * @rdev: radeon device structure * * Some R6XX/R7XX don't seem to take into account HDP flushes performed * through the ring buffer. This leads to corruption in rendering, see @@ -4390,10 +4390,9 @@ void r600_mmio_hdp_flush(struct radeon_device *rdev) if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) { void __iomem *ptr = (void *)rdev->vram_scratch.ptr; - u32 tmp; WREG32(HDP_DEBUG1, 0); - tmp = readl((void __iomem *)ptr); + readl((void __iomem *)ptr); } else WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1); } |