diff options
Diffstat (limited to 'drivers/gpu/drm/msm/dsi')
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/dsi.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/dsi.xml.h | 230 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/dsi_cfg.c | 21 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/dsi_host.c | 41 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/mmss_cc.xml.h | 26 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c | 18 | ||||
| -rw-r--r-- | drivers/gpu/drm/msm/dsi/sfpb.xml.h | 26 |
10 files changed, 298 insertions, 70 deletions
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index 55ea4bc2ee9c..627048851d99 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -161,6 +161,8 @@ static const struct of_device_id dt_match[] = { static const struct dev_pm_ops dsi_pm_ops = { SET_RUNTIME_PM_OPS(msm_dsi_runtime_suspend, msm_dsi_runtime_resume, NULL) + SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, + pm_runtime_force_resume) }; static struct platform_driver dsi_driver = { diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index 21f489a737d7..8e536e060070 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13) - -Copyright (C) 2013-2018 by the following authors: +- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14) + +Copyright (C) 2013-2020 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) @@ -148,7 +148,31 @@ static inline uint32_t DSI_6G_HW_VERSION_STEP(uint32_t val) #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000 #define REG_DSI_FIFO_STATUS 0x00000008 +#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_OVERFLOW 0x00000001 +#define DSI_FIFO_STATUS_VIDEO_MDP_FIFO_UNDERFLOW 0x00000008 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080 +#define DSI_FIFO_STATUS_CMD_DMA_FIFO_RD_WATERMARK_REACH 0x00000100 +#define DSI_FIFO_STATUS_CMD_DMA_FIFO_WR_WATERMARK_REACH 0x00000200 +#define DSI_FIFO_STATUS_CMD_DMA_FIFO_UNDERFLOW 0x00000400 +#define DSI_FIFO_STATUS_DLN0_LP_FIFO_EMPTY 0x00001000 +#define DSI_FIFO_STATUS_DLN0_LP_FIFO_FULL 0x00002000 +#define DSI_FIFO_STATUS_DLN0_LP_FIFO_OVERFLOW 0x00004000 +#define DSI_FIFO_STATUS_DLN0_HS_FIFO_EMPTY 0x00010000 +#define DSI_FIFO_STATUS_DLN0_HS_FIFO_FULL 0x00020000 +#define DSI_FIFO_STATUS_DLN0_HS_FIFO_OVERFLOW 0x00040000 +#define DSI_FIFO_STATUS_DLN0_HS_FIFO_UNDERFLOW 0x00080000 +#define DSI_FIFO_STATUS_DLN1_HS_FIFO_EMPTY 0x00100000 +#define DSI_FIFO_STATUS_DLN1_HS_FIFO_FULL 0x00200000 +#define DSI_FIFO_STATUS_DLN1_HS_FIFO_OVERFLOW 0x00400000 +#define DSI_FIFO_STATUS_DLN1_HS_FIFO_UNDERFLOW 0x00800000 +#define DSI_FIFO_STATUS_DLN2_HS_FIFO_EMPTY 0x01000000 +#define DSI_FIFO_STATUS_DLN2_HS_FIFO_FULL 0x02000000 +#define DSI_FIFO_STATUS_DLN2_HS_FIFO_OVERFLOW 0x04000000 +#define DSI_FIFO_STATUS_DLN2_HS_FIFO_UNDERFLOW 0x08000000 +#define DSI_FIFO_STATUS_DLN3_HS_FIFO_EMPTY 0x10000000 +#define DSI_FIFO_STATUS_DLN3_HS_FIFO_FULL 0x20000000 +#define DSI_FIFO_STATUS_DLN3_HS_FIFO_OVERFLOW 0x40000000 +#define DSI_FIFO_STATUS_DLN3_HS_FIFO_UNDERFLOW 0x80000000 #define REG_DSI_VID_CFG0 0x0000000c #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003 @@ -318,38 +342,72 @@ static inline uint32_t DSI_CMD_CFG1_WR_MEM_CONTINUE(uint32_t val) #define REG_DSI_DMA_LEN 0x00000048 -#define REG_DSI_CMD_MDP_STREAM_CTRL 0x00000054 -#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK 0x0000003f -#define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT 0 -static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE(uint32_t val) +#define REG_DSI_CMD_MDP_STREAM0_CTRL 0x00000054 +#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK 0x0000003f +#define DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT 0 +static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(uint32_t val) { - return ((val) << DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK; + return ((val) << DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE__MASK; } -#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 -#define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT 8 -static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL(uint32_t val) +#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 +#define DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT 8 +static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(uint32_t val) { - return ((val) << DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK; + return ((val) << DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL__MASK; } -#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK 0xffff0000 -#define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT 16 -static inline uint32_t DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(uint32_t val) +#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK 0xffff0000 +#define DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT 16 +static inline uint32_t DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(uint32_t val) { - return ((val) << DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK; + return ((val) << DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT__MASK; } -#define REG_DSI_CMD_MDP_STREAM_TOTAL 0x00000058 -#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK 0x00000fff -#define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT 0 -static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(uint32_t val) +#define REG_DSI_CMD_MDP_STREAM0_TOTAL 0x00000058 +#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK 0x00000fff +#define DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT 0 +static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(uint32_t val) { - return ((val) << DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK; + return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL__MASK; } -#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK 0x0fff0000 -#define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT 16 -static inline uint32_t DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(uint32_t val) +#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK 0x0fff0000 +#define DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT 16 +static inline uint32_t DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(uint32_t val) { - return ((val) << DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK; + return ((val) << DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL__MASK; +} + +#define REG_DSI_CMD_MDP_STREAM1_CTRL 0x0000005c +#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK 0x0000003f +#define DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT 0 +static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE(uint32_t val) +{ + return ((val) << DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_DATA_TYPE__MASK; +} +#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 +#define DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT 8 +static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL(uint32_t val) +{ + return ((val) << DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_VIRTUAL_CHANNEL__MASK; +} +#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK 0xffff0000 +#define DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT 16 +static inline uint32_t DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT(uint32_t val) +{ + return ((val) << DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MDP_STREAM1_CTRL_WORD_COUNT__MASK; +} + +#define REG_DSI_CMD_MDP_STREAM1_TOTAL 0x00000060 +#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK 0x0000ffff +#define DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT 0 +static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL(uint32_t val) +{ + return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_H_TOTAL__MASK; +} +#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK 0xffff0000 +#define DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT 16 +static inline uint32_t DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL(uint32_t val) +{ + return ((val) << DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__SHIFT) & DSI_CMD_MDP_STREAM1_TOTAL_V_TOTAL__MASK; } #define REG_DSI_ACK_ERR_STATUS 0x00000064 @@ -389,6 +447,35 @@ static inline uint32_t DSI_TRIG_CTRL_STREAM(uint32_t val) #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000 +#define REG_DSI_LP_TIMER_CTRL 0x000000b4 +#define DSI_LP_TIMER_CTRL_LP_RX_TO__MASK 0x0000ffff +#define DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT 0 +static inline uint32_t DSI_LP_TIMER_CTRL_LP_RX_TO(uint32_t val) +{ + return ((val) << DSI_LP_TIMER_CTRL_LP_RX_TO__SHIFT) & DSI_LP_TIMER_CTRL_LP_RX_TO__MASK; +} +#define DSI_LP_TIMER_CTRL_BTA_TO__MASK 0xffff0000 +#define DSI_LP_TIMER_CTRL_BTA_TO__SHIFT 16 +static inline uint32_t DSI_LP_TIMER_CTRL_BTA_TO(uint32_t val) +{ + return ((val) << DSI_LP_TIMER_CTRL_BTA_TO__SHIFT) & DSI_LP_TIMER_CTRL_BTA_TO__MASK; +} + +#define REG_DSI_HS_TIMER_CTRL 0x000000b8 +#define DSI_HS_TIMER_CTRL_HS_TX_TO__MASK 0x0000ffff +#define DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT 0 +static inline uint32_t DSI_HS_TIMER_CTRL_HS_TX_TO(uint32_t val) +{ + return ((val) << DSI_HS_TIMER_CTRL_HS_TX_TO__SHIFT) & DSI_HS_TIMER_CTRL_HS_TX_TO__MASK; +} +#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK 0x000f0000 +#define DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT 16 +static inline uint32_t DSI_HS_TIMER_CTRL_TIMER_RESOLUTION(uint32_t val) +{ + return ((val) << DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__SHIFT) & DSI_HS_TIMER_CTRL_TIMER_RESOLUTION__MASK; +} +#define DSI_HS_TIMER_CTRL_HS_TX_TO_STOP_EN 0x10000000 + #define REG_DSI_TIMEOUT_STATUS 0x000000bc #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0 @@ -409,6 +496,19 @@ static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val) #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010 +#define REG_DSI_LANE_STATUS 0x000000a4 +#define DSI_LANE_STATUS_DLN0_STOPSTATE 0x00000001 +#define DSI_LANE_STATUS_DLN1_STOPSTATE 0x00000002 +#define DSI_LANE_STATUS_DLN2_STOPSTATE 0x00000004 +#define DSI_LANE_STATUS_DLN3_STOPSTATE 0x00000008 +#define DSI_LANE_STATUS_CLKLN_STOPSTATE 0x00000010 +#define DSI_LANE_STATUS_DLN0_ULPS_ACTIVE_NOT 0x00000100 +#define DSI_LANE_STATUS_DLN1_ULPS_ACTIVE_NOT 0x00000200 +#define DSI_LANE_STATUS_DLN2_ULPS_ACTIVE_NOT 0x00000400 +#define DSI_LANE_STATUS_DLN3_ULPS_ACTIVE_NOT 0x00000800 +#define DSI_LANE_STATUS_CLKLN_ULPS_ACTIVE_NOT 0x00001000 +#define DSI_LANE_STATUS_DLN0_DIRECTION 0x00010000 + #define REG_DSI_LANE_CTRL 0x000000a8 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000 @@ -436,6 +536,21 @@ static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200 #define REG_DSI_CLK_STATUS 0x0000011c +#define DSI_CLK_STATUS_DSI_AON_AHBM_HCLK_ACTIVE 0x00000001 +#define DSI_CLK_STATUS_DSI_DYN_AHBM_HCLK_ACTIVE 0x00000002 +#define DSI_CLK_STATUS_DSI_AON_AHBS_HCLK_ACTIVE 0x00000004 +#define DSI_CLK_STATUS_DSI_DYN_AHBS_HCLK_ACTIVE 0x00000008 +#define DSI_CLK_STATUS_DSI_AON_DSICLK_ACTIVE 0x00000010 +#define DSI_CLK_STATUS_DSI_DYN_DSICLK_ACTIVE 0x00000020 +#define DSI_CLK_STATUS_DSI_AON_BYTECLK_ACTIVE 0x00000040 +#define DSI_CLK_STATUS_DSI_DYN_BYTECLK_ACTIVE 0x00000080 +#define DSI_CLK_STATUS_DSI_AON_ESCCLK_ACTIVE 0x00000100 +#define DSI_CLK_STATUS_DSI_AON_PCLK_ACTIVE 0x00000200 +#define DSI_CLK_STATUS_DSI_DYN_PCLK_ACTIVE 0x00000400 +#define DSI_CLK_STATUS_DSI_DYN_CMD_PCLK_ACTIVE 0x00001000 +#define DSI_CLK_STATUS_DSI_CMD_PCLK_ACTIVE 0x00002000 +#define DSI_CLK_STATUS_DSI_VID_PCLK_ACTIVE 0x00004000 +#define DSI_CLK_STATUS_DSI_CAM_BIST_PCLK_ACT 0x00008000 #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000 #define REG_DSI_PHY_RESET 0x00000128 @@ -444,6 +559,51 @@ static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum dsi_lane_swap val) #define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001 +#define REG_DSI_CMD_MODE_MDP_CTRL2 0x000001b4 +#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK 0x0000000f +#define DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT 0 +static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2(enum dsi_cmd_dst_format val) +{ + return ((val) << DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_DST_FORMAT2__MASK; +} +#define DSI_CMD_MODE_MDP_CTRL2_R_SEL 0x00000010 +#define DSI_CMD_MODE_MDP_CTRL2_G_SEL 0x00000020 +#define DSI_CMD_MODE_MDP_CTRL2_B_SEL 0x00000040 +#define DSI_CMD_MODE_MDP_CTRL2_BYTE_MSB_LSB_FLIP 0x00000080 +#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK 0x00000700 +#define DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT 8 +static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP(enum dsi_rgb_swap val) +{ + return ((val) << DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_RGB_SWAP__MASK; +} +#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK 0x00007000 +#define DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT 12 +static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap val) +{ + return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK; +} +#define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000 + +#define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8 +#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f +#define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT 0 +static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE(uint32_t val) +{ + return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK; +} +#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300 +#define DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT 8 +static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL(uint32_t val) +{ + return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_VIRTUAL_CHANNEL__MASK; +} +#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK 0xffff0000 +#define DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT 16 +static inline uint32_t DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT(uint32_t val) +{ + return ((val) << DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__SHIFT) & DSI_CMD_MODE_MDP_STREAM2_CTRL_WORD_COUNT__MASK; +} + #define REG_DSI_RDBK_DATA_CTRL 0x000001d0 #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000 #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT 16 diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index 813d69deb5e8..f892f2cbe8bb 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -149,6 +149,25 @@ static const struct msm_dsi_config msm8998_dsi_cfg = { .num_dsi = 2, }; +static const char * const dsi_sdm660_bus_clk_names[] = { + "iface", "bus", "core", "core_mmss", +}; + +static const struct msm_dsi_config sdm660_dsi_cfg = { + .io_offset = DSI_6G_REG_SHIFT, + .reg_cfg = { + .num = 2, + .regs = { + {"vdd", 73400, 32 }, /* 0.9 V */ + {"vdda", 12560, 4 }, /* 1.2 V */ + }, + }, + .bus_clk_names = dsi_sdm660_bus_clk_names, + .num_bus_clks = ARRAY_SIZE(dsi_sdm660_bus_clk_names), + .io_start = { 0xc994000, 0xc996000 }, + .num_dsi = 2, +}; + static const char * const dsi_sdm845_bus_clk_names[] = { "iface", "bus", }; @@ -240,6 +259,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { &msm8996_dsi_cfg, &msm_dsi_6g_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_4_2, &msm8976_dsi_cfg, &msm_dsi_6g_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_1_0, + &sdm660_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_0, &msm8998_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1, diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index 217e24a65178..efd469d1db45 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -18,6 +18,7 @@ #define MSM_DSI_6G_VER_MINOR_V1_3_1 0x10030001 #define MSM_DSI_6G_VER_MINOR_V1_4_1 0x10040001 #define MSM_DSI_6G_VER_MINOR_V1_4_2 0x10040002 +#define MSM_DSI_6G_VER_MINOR_V2_1_0 0x20010000 #define MSM_DSI_6G_VER_MINOR_V2_2_0 0x20000000 #define MSM_DSI_6G_VER_MINOR_V2_2_1 0x20020001 #define MSM_DSI_6G_VER_MINOR_V2_4_1 0x20040001 diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 66ca0c009cfa..b17ac6c27554 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -14,6 +14,7 @@ #include <linux/of_graph.h> #include <linux/of_irq.h> #include <linux/pinctrl/consumer.h> +#include <linux/pm_opp.h> #include <linux/regmap.h> #include <linux/regulator/consumer.h> #include <linux/spinlock.h> @@ -111,6 +112,9 @@ struct msm_dsi_host { struct clk *pixel_clk_src; struct clk *byte_intf_clk; + struct opp_table *opp_table; + bool has_opp_table; + u32 byte_clk_rate; u32 pixel_clk_rate; u32 esc_clk_rate; @@ -512,9 +516,10 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) DBG("Set clk rates: pclk=%d, byteclk=%d", msm_host->mode->clock, msm_host->byte_clk_rate); - ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); + ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, + msm_host->byte_clk_rate); if (ret) { - pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); + pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); return ret; } @@ -658,6 +663,8 @@ error: void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) { + /* Drop the performance state vote */ + dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); clk_disable_unprepare(msm_host->esc_clk); clk_disable_unprepare(msm_host->pixel_clk); if (msm_host->byte_intf_clk) @@ -986,16 +993,16 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) /* image data and 1 byte write_memory_start cmd */ wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; - dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_CTRL, - DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT(wc) | - DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL( + dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, + DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | + DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( msm_host->channel) | - DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE( + DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( MIPI_DSI_DCS_LONG_WRITE)); - dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM_TOTAL, - DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL(hdisplay) | - DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL(mode->vdisplay)); + dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, + DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | + DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); } } @@ -1879,6 +1886,19 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi) goto fail; } + msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "byte"); + if (IS_ERR(msm_host->opp_table)) + return PTR_ERR(msm_host->opp_table); + /* OPP table is optional */ + ret = dev_pm_opp_of_add_table(&pdev->dev); + if (!ret) { + msm_host->has_opp_table = true; + } else if (ret != -ENODEV) { + dev_err(&pdev->dev, "invalid OPP table in device tree\n"); + dev_pm_opp_put_clkname(msm_host->opp_table); + return ret; + } + init_completion(&msm_host->dma_comp); init_completion(&msm_host->video_comp); mutex_init(&msm_host->dev_mutex); @@ -1914,6 +1934,9 @@ void msm_dsi_host_destroy(struct mipi_dsi_host *host) mutex_destroy(&msm_host->cmd_mutex); mutex_destroy(&msm_host->dev_mutex); + if (msm_host->has_opp_table) + dev_pm_opp_of_remove_table(&msm_host->pdev->dev); + dev_pm_opp_put_clkname(msm_host->opp_table); pm_runtime_disable(&msm_host->pdev->dev); } diff --git a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h index 874265314413..4e8660c3eb08 100644 --- a/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h +++ b/drivers/gpu/drm/msm/dsi/mmss_cc.xml.h @@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13) - -Copyright (C) 2013-2018 by the following authors: +- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14) + +Copyright (C) 2013-2020 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index f509ebd77500..009f5b843dd1 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -499,6 +499,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { #ifdef CONFIG_DRM_MSM_DSI_14NM_PHY { .compatible = "qcom,dsi-phy-14nm", .data = &dsi_phy_14nm_cfgs }, + { .compatible = "qcom,dsi-phy-14nm-660", + .data = &dsi_phy_14nm_660_cfgs }, #endif #ifdef CONFIG_DRM_MSM_DSI_10NM_PHY { .compatible = "qcom,dsi-phy-10nm", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 24b294ed3059..ef8672d7b123 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -45,6 +45,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c index 1594f1422372..519400501bcd 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_14nm.c @@ -161,3 +161,21 @@ const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs = { .io_start = { 0x994400, 0x996400 }, .num_dsi_phy = 2, }; + +const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs = { + .type = MSM_DSI_PHY_14NM, + .src_pll_truthtable = { {false, false}, {true, false} }, + .reg_cfg = { + .num = 1, + .regs = { + {"vcca", 17000, 32}, + }, + }, + .ops = { + .enable = dsi_14nm_phy_enable, + .disable = dsi_14nm_phy_disable, + .init = dsi_14nm_phy_init, + }, + .io_start = { 0xc994400, 0xc996000 }, + .num_dsi_phy = 2, +}; diff --git a/drivers/gpu/drm/msm/dsi/sfpb.xml.h b/drivers/gpu/drm/msm/dsi/sfpb.xml.h index 07c48ddb5301..a3849220fc6a 100644 --- a/drivers/gpu/drm/msm/dsi/sfpb.xml.h +++ b/drivers/gpu/drm/msm/dsi/sfpb.xml.h @@ -8,19 +8,19 @@ http://github.com/freedreno/envytools/ git clone https://github.com/freedreno/envytools.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 37239 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41799 bytes, from 2018-07-03 19:37:13) -- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2018-07-03 19:37:13) - -Copyright (C) 2013-2018 by the following authors: +- /home/robclark/src/envytools/rnndb/msm.xml ( 676 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/mdp/mdp_common.xml ( 2849 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/mdp/mdp5.xml ( 37411 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/dsi/dsi.xml ( 42301 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/dsi/sfpb.xml ( 602 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/hdmi/hdmi.xml ( 41874 bytes, from 2020-07-23 21:58:14) +- /home/robclark/src/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2020-07-23 21:58:14) + +Copyright (C) 2013-2020 by the following authors: - Rob Clark <robdclark@gmail.com> (robclark) - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) |