diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/include')
9 files changed, 76 insertions, 16 deletions
diff --git a/drivers/gpu/drm/amd/display/include/audio_types.h b/drivers/gpu/drm/amd/display/include/audio_types.h index 6364fbc24cfe..66a54da0641c 100644 --- a/drivers/gpu/drm/amd/display/include/audio_types.h +++ b/drivers/gpu/drm/amd/display/include/audio_types.h @@ -38,8 +38,8 @@ struct audio_crtc_info { uint32_t h_active; uint32_t v_active; uint32_t pixel_repetition; - uint32_t requested_pixel_clock; /* in KHz */ - uint32_t calculated_pixel_clock; /* in KHz */ + uint32_t requested_pixel_clock_100Hz; /* in 100Hz */ + uint32_t calculated_pixel_clock_100Hz; /* in 100Hz */ uint32_t refresh_rate; enum dc_color_depth color_depth; bool interlaced; diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h index 887e6a8597c4..1be6c44fd32f 100644 --- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h +++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h @@ -137,10 +137,13 @@ #define RAVEN1_F0 0xF0 #define RAVEN_UNKNOWN 0xFF +#define PICASSO_15D8_REV_E3 0xE3 +#define PICASSO_15D8_REV_E4 0xE4 + #define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN) #define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0)) -#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < 0xF0)) - +#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < PICASSO_15D8_REV_E3)) +#define ASICREV_IS_DALI(eChipRev) ((eChipRev >= PICASSO_15D8_REV_E3) && (eChipRev < RAVEN1_F0)) #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN)) @@ -151,6 +154,21 @@ #define FAMILY_NV 143 /* DCN 2*/ +enum { + NV_NAVI10_P_A0 = 1, + NV_NAVI12_P_A0 = 10, + NV_NAVI14_M_A0 = 20, + NV_UNKNOWN = 0xFF +}; + +#define ASICREV_IS_NAVI10_P(eChipRev) (eChipRev < NV_NAVI12_P_A0) +#define ASICREV_IS_NAVI12_P(eChipRev) ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0)) +#define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN)) +#endif +#if defined(CONFIG_DRM_AMD_DC_DCN2_1) +#define RENOIR_A0 0x91 +#define DEVICE_ID_RENOIR_1636 0x1636 // Renoir +#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < 0xFF)) #endif /* diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h index 1e3ce4d847ae..fcc42372b6cf 100644 --- a/drivers/gpu/drm/amd/display/include/dal_types.h +++ b/drivers/gpu/drm/amd/display/include/dal_types.h @@ -49,6 +49,9 @@ enum dce_version { #if defined(CONFIG_DRM_AMD_DC_DCN2_0) DCN_VERSION_2_0, #endif +#if defined(CONFIG_DRM_AMD_DC_DCN2_1) + DCN_VERSION_2_1, +#endif DCN_VERSION_MAX }; diff --git a/drivers/gpu/drm/amd/display/include/ddc_service_types.h b/drivers/gpu/drm/amd/display/include/ddc_service_types.h index d968956a10cd..18961707db23 100644 --- a/drivers/gpu/drm/amd/display/include/ddc_service_types.h +++ b/drivers/gpu/drm/amd/display/include/ddc_service_types.h @@ -25,10 +25,12 @@ #ifndef __DAL_DDC_SERVICE_TYPES_H__ #define __DAL_DDC_SERVICE_TYPES_H__ -#define DP_BRANCH_DEVICE_ID_1 0x0010FA -#define DP_BRANCH_DEVICE_ID_2 0x0022B9 -#define DP_BRANCH_DEVICE_ID_3 0x00001A -#define DP_BRANCH_DEVICE_ID_4 0x0080e1 +/* 0010FA dongles (ST Micro) external converter chip id */ +#define DP_BRANCH_DEVICE_ID_0010FA 0x0010FA +/* 0022B9 external converter chip id */ +#define DP_BRANCH_DEVICE_ID_0022B9 0x0022B9 +#define DP_BRANCH_DEVICE_ID_00001A 0x00001A +#define DP_BRANCH_DEVICE_ID_0080E1 0x0080e1 enum ddc_result { DDC_RESULT_UNKNOWN = 0, diff --git a/drivers/gpu/drm/amd/display/include/gpio_interface.h b/drivers/gpu/drm/amd/display/include/gpio_interface.h index 7de64195dc33..5e888a093c16 100644 --- a/drivers/gpu/drm/amd/display/include/gpio_interface.h +++ b/drivers/gpu/drm/amd/display/include/gpio_interface.h @@ -93,8 +93,17 @@ enum sync_source dal_gpio_get_sync_source( enum gpio_pin_output_state dal_gpio_get_output_state( const struct gpio *gpio); +struct hw_ddc *dal_gpio_get_ddc(struct gpio *gpio); + +struct hw_hpd *dal_gpio_get_hpd(struct gpio *gpio); + +struct hw_generic *dal_gpio_get_generic(struct gpio *gpio); + /* Close the handle */ void dal_gpio_close( struct gpio *gpio); + + + #endif diff --git a/drivers/gpu/drm/amd/display/include/gpio_service_interface.h b/drivers/gpu/drm/amd/display/include/gpio_service_interface.h index f40259bade40..9c55d247227e 100644 --- a/drivers/gpu/drm/amd/display/include/gpio_service_interface.h +++ b/drivers/gpu/drm/amd/display/include/gpio_service_interface.h @@ -51,13 +51,29 @@ struct gpio *dal_gpio_service_create_irq( uint32_t offset, uint32_t mask); +struct gpio *dal_gpio_service_create_generic_mux( + struct gpio_service *service, + uint32_t offset, + uint32_t mask); + +void dal_gpio_destroy_generic_mux( + struct gpio **mux); + +enum gpio_result dal_mux_setup_config( + struct gpio *mux, + struct gpio_generic_mux_config *config); + +struct gpio_pin_info dal_gpio_get_generic_pin_info( + struct gpio_service *service, + enum gpio_id id, + uint32_t en); + struct ddc *dal_gpio_create_ddc( struct gpio_service *service, uint32_t offset, uint32_t mask, struct gpio_ddc_hw_info *info); - void dal_gpio_destroy_ddc( struct ddc **ddc); diff --git a/drivers/gpu/drm/amd/display/include/link_service_types.h b/drivers/gpu/drm/amd/display/include/link_service_types.h index 80f0d93cfd94..876b0b3e1a9c 100644 --- a/drivers/gpu/drm/amd/display/include/link_service_types.h +++ b/drivers/gpu/drm/amd/display/include/link_service_types.h @@ -71,14 +71,17 @@ enum link_training_result { struct link_training_settings { struct dc_link_settings link_settings; struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; - bool allow_invalid_msa_timing_param; -}; -enum hw_dp_training_pattern { - HW_DP_TRAINING_PATTERN_1 = 0, - HW_DP_TRAINING_PATTERN_2, - HW_DP_TRAINING_PATTERN_3, - HW_DP_TRAINING_PATTERN_4 + enum dc_voltage_swing *voltage_swing; + enum dc_pre_emphasis *pre_emphasis; + enum dc_post_cursor2 *post_cursor2; + + uint16_t cr_pattern_time; + uint16_t eq_pattern_time; + enum dc_dp_training_pattern pattern_for_eq; + + bool enhanced_framing; + bool allow_invalid_msa_timing_param; }; /*TODO: Move this enum test harness*/ diff --git a/drivers/gpu/drm/amd/display/include/logger_interface.h b/drivers/gpu/drm/amd/display/include/logger_interface.h index a0b68c266dab..6e008de25629 100644 --- a/drivers/gpu/drm/amd/display/include/logger_interface.h +++ b/drivers/gpu/drm/amd/display/include/logger_interface.h @@ -155,4 +155,6 @@ void context_clock_trace( #define DISPLAY_STATS_END(entry) (void)(entry) +#define LOG_GAMMA_WRITE(msg, ...) + #endif /* __DAL_LOGGER_INTERFACE_H__ */ diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h index ea8d445816b8..2b219cdb13ad 100644 --- a/drivers/gpu/drm/amd/display/include/logger_types.h +++ b/drivers/gpu/drm/amd/display/include/logger_types.h @@ -63,6 +63,9 @@ #define DC_LOG_IF_TRACE(...) pr_debug("[IF_TRACE]:"__VA_ARGS__) #define DC_LOG_PERF_TRACE(...) DRM_DEBUG_KMS(__VA_ARGS__) #define DC_LOG_RETIMER_REDRIVER(...) DRM_DEBUG_KMS(__VA_ARGS__) +#define DC_LOG_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__) +#define DC_LOG_ALL_GAMMA(...) pr_debug("[GAMMA]:"__VA_ARGS__) +#define DC_LOG_ALL_TF_CHANNELS(...) pr_debug("[GAMMA]:"__VA_ARGS__) #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define DC_LOG_DSC(...) DRM_DEBUG_KMS(__VA_ARGS__) #endif @@ -117,6 +120,10 @@ enum dc_log_type { LOG_DSC, #endif LOG_DWB, + LOG_GAMMA_DEBUG, + LOG_MAX_HW_POINTS, + LOG_ALL_TF_CHANNELS, + LOG_SAMPLE_1DLUT, LOG_SECTION_TOTAL_COUNT }; |