diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h index bf40725f982f..f91e85b04956 100644 --- a/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h +++ b/drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h @@ -48,6 +48,14 @@ DDC_GPIO_REG_LIST(cd,id),\ .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP) +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + #define DDC_REG_LIST_DCN2(cd, id) \ + DDC_GPIO_REG_LIST(cd, id),\ + .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\ + .phy_aux_cntl = REG(PHY_AUX_CNTL), \ + .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) +#endif + #define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\ .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\ .type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\ @@ -82,6 +90,13 @@ DDC_GPIO_I2C_REG_LIST(cd),\ .ddc_setup = 0 +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) +#define DDC_I2C_REG_LIST_DCN2(cd) \ + DDC_GPIO_I2C_REG_LIST(cd),\ + .ddc_setup = 0,\ + .phy_aux_cntl = REG(PHY_AUX_CNTL), \ + .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) +#endif #define DDC_MASK_SH_LIST_COMMON(mask_sh) \ SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\ SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\ @@ -95,10 +110,22 @@ SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\ SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh) +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) +#define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \ + {DDC_MASK_SH_LIST_COMMON(mask_sh),\ + 0,\ + 0,\ + (PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\ + (DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)} +#endif struct ddc_registers { struct gpio_registers gpio; uint32_t ddc_setup; +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + uint32_t phy_aux_cntl; + uint32_t dc_gpio_aux_ctrl_5; +#endif }; struct ddc_sh_mask { @@ -113,6 +140,11 @@ struct ddc_sh_mask { /* i2cpad_mask */ uint32_t DC_GPIO_SDA_PD_DIS; uint32_t DC_GPIO_SCL_PD_DIS; +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + //phy_aux_cntl + uint32_t AUX_PAD_RXSEL; + uint32_t DDC_PAD_I2CMODE; +#endif }; @@ -148,6 +180,27 @@ struct ddc_sh_mask { {\ DDC_I2C_REG_LIST(SCL)\ } +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) +#define ddc_data_regs_dcn2(id) \ +{\ + DDC_REG_LIST_DCN2(DATA, id)\ +} + +#define ddc_clk_regs_dcn2(id) \ +{\ + DDC_REG_LIST_DCN2(CLK, id)\ +} + +#define ddc_i2c_data_regs_dcn2 \ +{\ + DDC_I2C_REG_LIST_DCN2(SDA)\ +} + +#define ddc_i2c_clk_regs_dcn2 \ +{\ + DDC_REG_LIST_DCN2(SCL)\ +} +#endif #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */ |