diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c | 39 |
1 files changed, 18 insertions, 21 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c index f5bcffc426b8..5ab9d6240498 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_stream_encoder.c @@ -207,9 +207,8 @@ static void enc2_stream_encoder_stop_hdmi_info_packets( #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT - /* Update GSP7 SDP 128 byte long */ -static void enc2_send_gsp7_128_info_packet( +static void enc2_update_gsp7_128_info_packet( struct dcn10_stream_encoder *enc1, const struct dc_info_packet_128 *info_packet) { @@ -277,18 +276,9 @@ static void enc2_send_gsp7_128_info_packet( static void enc2_dp_set_dsc_config(struct stream_encoder *enc, enum optc_dsc_mode dsc_mode, uint32_t dsc_bytes_per_pixel, - uint32_t dsc_slice_width, - uint8_t *dsc_packed_pps) + uint32_t dsc_slice_width) { struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - uint32_t dsc_value = 0; - - dsc_value = REG_READ(DP_DSC_CNTL); - - /* dsc disable skip */ - if ((dsc_value & 0x3) == 0x0) - return; - REG_UPDATE_2(DP_DSC_CNTL, DP_DSC_MODE, dsc_mode, @@ -296,8 +286,16 @@ static void enc2_dp_set_dsc_config(struct stream_encoder *enc, REG_SET(DP_DSC_BYTES_PER_PIXEL, 0, DP_DSC_BYTES_PER_PIXEL, dsc_bytes_per_pixel); +} + + +static void enc2_dp_set_dsc_pps_info_packet(struct stream_encoder *enc, + bool enable, + uint8_t *dsc_packed_pps) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); - if (dsc_mode != OPTC_DSC_DISABLED) { + if (enable) { struct dc_info_packet_128 pps_sdp; ASSERT(dsc_packed_pps); @@ -309,7 +307,7 @@ static void enc2_dp_set_dsc_config(struct stream_encoder *enc, pps_sdp.hb2 = 127; pps_sdp.hb3 = 0; memcpy(&pps_sdp.sb[0], dsc_packed_pps, sizeof(pps_sdp.sb)); - enc2_send_gsp7_128_info_packet(enc1, &pps_sdp); + enc2_update_gsp7_128_info_packet(enc1, &pps_sdp); /* Enable Generic Stream Packet 7 (GSP) transmission */ //REG_UPDATE(DP_SEC_CNTL, @@ -340,9 +338,8 @@ static void enc2_dp_set_dsc_config(struct stream_encoder *enc, REG_UPDATE(DP_SEC_CNTL2, DP_SEC_GSP7_PPS, 0); } } -#endif -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + /* this function read dsc related register fields to be logged later in dcn10_log_hw_state * into a dcn_dsc_state struct. */ @@ -373,7 +370,7 @@ static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s) * * Ensure the OTG master update lock is set when changing DME configuration. */ -static void enc2_set_dynamic_metadata(struct stream_encoder *enc, +void enc2_set_dynamic_metadata(struct stream_encoder *enc, bool enable_dme, uint32_t hubp_requestor_id, enum dynamic_metadata_mode dmdata_mode) @@ -463,7 +460,7 @@ void enc2_stream_encoder_dp_unblank( uint64_t m_vid_l = n_vid; /* YCbCr 4:2:0 : Computed VID_M will be 2X the input rate */ - if (is_two_pixels_per_containter(¶m->timing) || param->odm) { + if (is_two_pixels_per_containter(¶m->timing) || param->opp_cnt > 1) { /*this logic should be the same in get_pixel_clock_parameters() */ n_multiply = 1; } @@ -580,14 +577,14 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = { .setup_stereo_sync = enc1_setup_stereo_sync, .set_avmute = enc1_stream_encoder_set_avmute, .dig_connect_to_otg = enc1_dig_connect_to_otg, + .dig_source_otg = enc1_dig_source_otg, #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc2_read_state, -#endif - -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dp_set_dsc_config = enc2_dp_set_dsc_config, + .dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet, #endif .set_dynamic_metadata = enc2_set_dynamic_metadata, + .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, }; void dcn20_stream_encoder_construct( |