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path: root/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h16
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
index fb055e6883c0..2309f2bb162c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.h
@@ -95,6 +95,11 @@ enum {
SR(DC_I2C_DATA),\
SR(MICROSECOND_TIME_BASE_DIV)
+#define I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id)\
+ I2C_HW_ENGINE_COMMON_REG_LIST(id),\
+ SR(DIO_MEM_PWR_CTRL),\
+ SR(DIO_MEM_PWR_STATUS)
+
#define I2C_SF(reg_name, field_name, post_fix)\
.field_name = reg_name ## __ ## field_name ## post_fix
@@ -179,6 +184,8 @@ struct dce_i2c_shift {
uint8_t XTAL_REF_DIV;
uint8_t DC_I2C_DDC1_SEND_RESET_LENGTH;
uint8_t DC_I2C_REG_RW_CNTL_STATUS;
+ uint8_t I2C_LIGHT_SLEEP_FORCE;
+ uint8_t I2C_MEM_PWR_STATE;
};
struct dce_i2c_mask {
@@ -220,12 +227,19 @@ struct dce_i2c_mask {
uint32_t XTAL_REF_DIV;
uint32_t DC_I2C_DDC1_SEND_RESET_LENGTH;
uint32_t DC_I2C_REG_RW_CNTL_STATUS;
+ uint32_t I2C_LIGHT_SLEEP_FORCE;
+ uint32_t I2C_MEM_PWR_STATE;
};
#define I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh)\
I2C_COMMON_MASK_SH_LIST_DCE110(mask_sh),\
I2C_SF(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_SEND_RESET_LENGTH, mask_sh)
+#define I2C_COMMON_MASK_SH_LIST_DCN30(mask_sh)\
+ I2C_COMMON_MASK_SH_LIST_DCN2(mask_sh),\
+ I2C_SF(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh),\
+ I2C_SF(DIO_MEM_PWR_STATUS, I2C_MEM_PWR_STATE, mask_sh)
+
struct dce_i2c_registers {
uint32_t SETUP;
uint32_t SPEED;
@@ -239,6 +253,8 @@ struct dce_i2c_registers {
uint32_t DC_I2C_TRANSACTION3;
uint32_t DC_I2C_DATA;
uint32_t MICROSECOND_TIME_BASE_DIV;
+ uint32_t DIO_MEM_PWR_CTRL;
+ uint32_t DIO_MEM_PWR_STATUS;
};
enum dce_i2c_transaction_address_space {