path: root/drivers
diff options
authorTomi Valkeinen <>2019-10-02 15:25:42 +0300
committerTomi Valkeinen <>2019-10-03 09:45:01 +0300
commite2c4ed148cf3ec8669a1d90dc66966028e5fad70 (patch)
treeb16fbc46f3c50530cf69789e36cc2dbb8d9af545 /drivers
parenta0ecd6fdbf5d648123a7315c695fb6850d702835 (diff)
drm/omap: fix max fclk divider for omap36xx
The OMAP36xx and AM/DM37x TRMs say that the maximum divider for DSS fclk (in CM_CLKSEL_DSS) is 32. Experimentation shows that this is not correct, and using divider of 32 breaks DSS with a flood or underflows and sync losts. Dividers up to 31 seem to work fine. There is another patch to the DT files to limit the divider correctly, but as the DSS driver also needs to know the maximum divider to be able to iteratively find good rates, we also need to do the fix in the DSS driver. Signed-off-by: Tomi Valkeinen <> Cc: Adam Ford <> Cc: Link: Tested-by: Adam Ford <> Reviewed-by: Jyri Sarha <>
Diffstat (limited to 'drivers')
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/omapdrm/dss/dss.c b/drivers/gpu/drm/omapdrm/dss/dss.c
index 5711b7a720e6..25b6a79dc385 100644
--- a/drivers/gpu/drm/omapdrm/dss/dss.c
+++ b/drivers/gpu/drm/omapdrm/dss/dss.c
@@ -1090,7 +1090,7 @@ static const struct dss_features omap34xx_dss_feats = {
static const struct dss_features omap3630_dss_feats = {
.model = DSS_MODEL_OMAP3,
- .fck_div_max = 32,
+ .fck_div_max = 31,
.fck_freq_max = 173000000,
.dss_fck_multiplier = 1,
.parent_clk_name = "dpll4_ck",