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authorDave Airlie <airlied@redhat.com>2015-02-11 15:35:26 +1000
committerDave Airlie <airlied@redhat.com>2015-02-11 15:35:26 +1000
commit85840c76d8ad18d978da44e8d2f27bb35b7159af (patch)
treec54f837e30c81d4f30aa8eb6c9f6b764734dcd1b /drivers
parent79a44c16b155b799421f5497ae888985a5d7f80c (diff)
parenta49e7c0d079610062048a4ed1cff2bb09436127c (diff)
Merge tag 'imx-drm-fixes-2015-01-28' of git://git.pengutronix.de/git/pza/linux into drm-next
imx-drm fixes for IPUv3 DC and i.MX5 IPUv3 IC and TVE - Corrected handling of wait_for_completion_timeout return value when disabling IPUv3 DC channels - Fixed error return value propagation in TVE mode_set - Fixed IPUv3 register offsets for IC module on i.MX51 and i.MX53 * tag 'imx-drm-fixes-2015-01-28' of git://git.pengutronix.de/git/pza/linux: gpu: ipu-v3: Fix IC control register offset drm: imx: imx-tve: Check and propagate the errors gpu: ipu-v3: wait_for_completion_timeout does not return negative status
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/drm/imx/imx-tve.c24
-rw-r--r--drivers/gpu/ipu-v3/ipu-common.c4
-rw-r--r--drivers/gpu/ipu-v3/ipu-dc.c5
3 files changed, 21 insertions, 12 deletions
diff --git a/drivers/gpu/drm/imx/imx-tve.c b/drivers/gpu/drm/imx/imx-tve.c
index b63601d04601..4216e479a9be 100644
--- a/drivers/gpu/drm/imx/imx-tve.c
+++ b/drivers/gpu/drm/imx/imx-tve.c
@@ -191,10 +191,18 @@ static int tve_setup_vga(struct imx_tve *tve)
/* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
TVE_TVDAC_GAIN_MASK, 0x0a);
+ if (ret)
+ return ret;
+
ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
TVE_TVDAC_GAIN_MASK, 0x0a);
+ if (ret)
+ return ret;
+
ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
TVE_TVDAC_GAIN_MASK, 0x0a);
+ if (ret)
+ return ret;
/* set configuration register */
mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
@@ -204,16 +212,12 @@ static int tve_setup_vga(struct imx_tve *tve)
mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
- if (ret < 0) {
- dev_err(tve->dev, "failed to set configuration: %d\n", ret);
+ if (ret)
return ret;
- }
/* set test mode (as documented) */
- ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
+ return regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
TVE_TVDAC_TEST_MODE_MASK, 1);
-
- return 0;
}
static enum drm_connector_status imx_tve_connector_detect(
@@ -335,9 +339,11 @@ static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
}
if (tve->mode == TVE_MODE_VGA)
- tve_setup_vga(tve);
+ ret = tve_setup_vga(tve);
else
- tve_setup_tvout(tve);
+ ret = tve_setup_tvout(tve);
+ if (ret)
+ dev_err(tve->dev, "failed to set configuration: %d\n", ret);
}
static void imx_tve_encoder_commit(struct drm_encoder *encoder)
@@ -671,6 +677,8 @@ static int imx_tve_bind(struct device *dev, struct device *master, void *data)
/* disable cable detection for VGA mode */
ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
+ if (ret)
+ return ret;
ret = imx_tve_register(drm, tve);
if (ret)
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index f707d25ae78f..67bab5c36056 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -742,7 +742,7 @@ static struct ipu_devtype ipu_type_imx51 = {
.tpm_ofs = 0x1f060000,
.csi0_ofs = 0x1f030000,
.csi1_ofs = 0x1f038000,
- .ic_ofs = 0x1f020000,
+ .ic_ofs = 0x1e020000,
.disp0_ofs = 0x1e040000,
.disp1_ofs = 0x1e048000,
.dc_tmpl_ofs = 0x1f080000,
@@ -758,7 +758,7 @@ static struct ipu_devtype ipu_type_imx53 = {
.tpm_ofs = 0x07060000,
.csi0_ofs = 0x07030000,
.csi1_ofs = 0x07038000,
- .ic_ofs = 0x07020000,
+ .ic_ofs = 0x06020000,
.disp0_ofs = 0x06040000,
.disp1_ofs = 0x06048000,
.dc_tmpl_ofs = 0x07080000,
diff --git a/drivers/gpu/ipu-v3/ipu-dc.c b/drivers/gpu/ipu-v3/ipu-dc.c
index 323203d0503a..4864f8300797 100644
--- a/drivers/gpu/ipu-v3/ipu-dc.c
+++ b/drivers/gpu/ipu-v3/ipu-dc.c
@@ -277,7 +277,8 @@ static irqreturn_t dc_irq_handler(int irq, void *dev_id)
void ipu_dc_disable_channel(struct ipu_dc *dc)
{
struct ipu_dc_priv *priv = dc->priv;
- int irq, ret;
+ int irq;
+ unsigned long ret;
u32 val;
/* TODO: Handle MEM_FG_SYNC differently from MEM_BG_SYNC */
@@ -292,7 +293,7 @@ void ipu_dc_disable_channel(struct ipu_dc *dc)
enable_irq(irq);
ret = wait_for_completion_timeout(&priv->comp, msecs_to_jiffies(50));
disable_irq(irq);
- if (ret <= 0) {
+ if (ret == 0) {
dev_warn(priv->dev, "DC stop timeout after 50 ms\n");
val = readl(dc->base + DC_WR_CH_CONF);