diff options
| author | Jarkko Nikula <jarkko.nikula@linux.intel.com> | 2019-06-28 17:07:17 +0300 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2019-07-02 12:48:26 +0100 |
| commit | 23cdddb21f41e6092643fb8403f992f99ade33be (patch) | |
| tree | 23552554084a88560f57990caf1862310cfb5d77 /drivers/spi | |
| parent | 775c4c0032c408b8a57a3fc2695eeda101da003a (diff) | |
spi: pxa2xx: Set minimum transfer speed
It is possible to request a transfer with a speed lower than supported
by the HW. This causes silent divider calculation underflow in
ssp_get_clk_div() which leads to a frequency higher than requested. Up to
maximum speed of the controller.
Set the minimum supported transfer speed and let the SPI core to
validate no transfers have speed lower than supported.
Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi')
| -rw-r--r-- | drivers/spi/spi-pxa2xx.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index af3f37ba82c8..259c20f7a542 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -1704,6 +1704,16 @@ static int pxa2xx_spi_probe(struct platform_device *pdev) goto out_error_dma_irq_alloc; controller->max_speed_hz = clk_get_rate(ssp->clk); + /* + * Set minimum speed for all other platforms than Intel Quark which is + * able do under 1 Hz transfers. + */ + if (!pxa25x_ssp_comp(drv_data)) + controller->min_speed_hz = + DIV_ROUND_UP(controller->max_speed_hz, 4096); + else if (!is_quark_x1000_ssp(drv_data)) + controller->min_speed_hz = + DIV_ROUND_UP(controller->max_speed_hz, 512); /* Load default SSP configuration */ pxa2xx_spi_write(drv_data, SSCR0, 0); |