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authorAlison Wang <alison.wang@nxp.com>2018-04-24 10:42:32 +0800
committerLiviu Dudau <Liviu.Dudau@arm.com>2018-06-18 18:02:11 +0100
commit89610dc2c235e7b02bb9fba0ce247e12d4dde7cd (patch)
tree4e3bc4a4b0365113fe5670b773f71ac6981277bd /drivers/gpu
parent109c4d18e57445afcaf728b8716a69375a3daab2 (diff)
drm: mali-dp: Enable Global SE interrupts mask for DP500
In the situation that DE and SE aren’t shared the same interrupt number, the Global SE interrupts mask bit MASK_IRQ_EN in MASKIRQ must be set, or else other mask bits will not work and no SE interrupt will occur. This patch enables MASK_IRQ_EN for SE to fix this problem. Signed-off-by: Alison Wang <alison.wang@nxp.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/arm/malidp_hw.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/arm/malidp_hw.c b/drivers/gpu/drm/arm/malidp_hw.c
index d789b46dc817..069783e715f1 100644
--- a/drivers/gpu/drm/arm/malidp_hw.c
+++ b/drivers/gpu/drm/arm/malidp_hw.c
@@ -634,7 +634,8 @@ const struct malidp_hw malidp_device[MALIDP_MAX_DEVICES] = {
.vsync_irq = MALIDP500_DE_IRQ_VSYNC,
},
.se_irq_map = {
- .irq_mask = MALIDP500_SE_IRQ_CONF_MODE,
+ .irq_mask = MALIDP500_SE_IRQ_CONF_MODE |
+ MALIDP500_SE_IRQ_GLOBAL,
.vsync_irq = 0,
},
.dc_irq_map = {