summaryrefslogtreecommitdiff
path: root/drivers/gpu
diff options
context:
space:
mode:
authorBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>2020-05-21 12:28:39 -0400
committerAlex Deucher <alexander.deucher@amd.com>2020-07-01 01:59:14 -0400
commit7c40270be76d0ee33455bba728d508f5dddfc604 (patch)
tree3409ee2cd8f71942eb6ee43fddfb80bc52e8a9d1 /drivers/gpu
parent2c6e83a134b84c2257403ed2e4480b2f09673d3e (diff)
drm/amd/display: Add DCN3 chip ids
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/drm/amd/display/include/dal_asic_id.h4
-rw-r--r--drivers/gpu/drm/amd/display/include/dal_types.h1
2 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 2359e88d6029..abeb58d544b1 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -166,6 +166,7 @@ enum {
NV_NAVI10_P_A0 = 1,
NV_NAVI12_P_A0 = 10,
NV_NAVI14_M_A0 = 20,
+ NV_SIENNA_CICHLID_P_A0 = 40,
NV_UNKNOWN = 0xFF
};
@@ -173,6 +174,9 @@ enum {
#define ASICREV_IS_NAVI12_P(eChipRev) ((eChipRev >= NV_NAVI12_P_A0) && (eChipRev < NV_NAVI14_M_A0))
#define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0))
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0))
+#endif
/*
* ASIC chip ID
diff --git a/drivers/gpu/drm/amd/display/include/dal_types.h b/drivers/gpu/drm/amd/display/include/dal_types.h
index 0b6859189ca7..b67c9fa6b9cd 100644
--- a/drivers/gpu/drm/amd/display/include/dal_types.h
+++ b/drivers/gpu/drm/amd/display/include/dal_types.h
@@ -48,6 +48,7 @@ enum dce_version {
DCN_VERSION_1_01,
DCN_VERSION_2_0,
DCN_VERSION_2_1,
+ DCN_VERSION_3_0,
DCN_VERSION_MAX
};