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authorLucas Stach <l.stach@pengutronix.de>2017-05-03 18:16:46 +0200
committerPhilipp Zabel <p.zabel@pengutronix.de>2017-06-08 08:57:13 +0200
commit16e9ab820ad43108513ec32bb18fb226df4cc7fc (patch)
tree1761f4a225f9c8492213cf7ae2047b2e43951d6f /drivers/gpu/ipu-v3/ipu-prg.c
parent2ea659a9ef488125eb46da6eb571de5eae5c43f6 (diff)
gpu: ipu-v3: prg: remove counter load enable
The counter load enable bit has no effect when the shadow register set is activated. As we always operate the PRG with shadow enabled it is safe to remove this. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'drivers/gpu/ipu-v3/ipu-prg.c')
-rw-r--r--drivers/gpu/ipu-v3/ipu-prg.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/drivers/gpu/ipu-v3/ipu-prg.c b/drivers/gpu/ipu-v3/ipu-prg.c
index caca57febbd6..ecc9ea44dc50 100644
--- a/drivers/gpu/ipu-v3/ipu-prg.c
+++ b/drivers/gpu/ipu-v3/ipu-prg.c
@@ -318,8 +318,6 @@ int ipu_prg_channel_configure(struct ipuv3_channel *ipu_chan,
writel(val, prg->regs + IPU_PRG_BADDR(prg_chan));
val = readl(prg->regs + IPU_PRG_CTL);
- /* counter load enable */
- val |= IPU_PRG_CTL_CNT_LOAD_EN(prg_chan);
/* config AXI ID */
val &= ~(IPU_PRG_CTL_SOFT_ARID_MASK <<
IPU_PRG_CTL_SOFT_ARID_SHIFT(prg_chan));