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authorNathan Chancellor <natechancellor@gmail.com>2019-06-19 12:17:23 -0700
committerRob Clark <robdclark@chromium.org>2019-06-19 12:30:55 -0700
commit01a090c746697436aef0873c6f33ede44c517aec (patch)
treeaaf2fb2b2c8c44f84e53c0e91a1634edf3a3545b /drivers/gpu/drm
parent370063ee427ae77b07c6f5dbdced608ae2ce79de (diff)
drm/msm/dsi: Add parentheses to quirks check in dsi_phy_hw_v3_0_lane_settings
Clang warns: drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c:80:6: warning: logical not is only applied to the left hand side of this bitwise operator [-Wlogical-not-parentheses] if (!phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) { ^ ~ drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c:80:6: note: add parentheses after the '!' to evaluate the bitwise operator first if (!phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) { ^ ( ) drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c:80:6: note: add parentheses around left hand side expression to silence this warning if (!phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) { ^ ( ) 1 warning generated. Add parentheses around the bitwise AND so it is evaluated first then negated. Fixes: 3dbbf8f09e83 ("drm/msm/dsi: Add old timings quirk for 10nm phy") Link: https://github.com/ClangBuiltLinux/linux/issues/547 Reported-by: kbuild test robot <lkp@intel.com> Reviewed-by: Jeffrey Hugo <jeffrey.l.hugo@gmail.com> Reviewed-by: Sean Paul <sean@poorly.run> Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
Diffstat (limited to 'drivers/gpu/drm')
-rw-r--r--drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
index eb28937f4b34..47403d4f2d28 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_10nm.c
@@ -77,7 +77,7 @@ static void dsi_phy_hw_v3_0_lane_settings(struct msm_dsi_phy *phy)
tx_dctrl[i]);
}
- if (!phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK) {
+ if (!(phy->cfg->quirks & V3_0_0_10NM_OLD_TIMINGS_QUIRK)) {
/* Toggle BIT 0 to release freeze I/0 */
dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x05);
dsi_phy_write(lane_base + REG_DSI_10nm_PHY_LN_TX_DCTRL(3), 0x04);