path: root/drivers/gpu/drm/msm/dsi/pll
diff options
authorJerome Brunet <>2017-12-21 17:30:54 +0100
committerStephen Boyd <>2017-12-28 15:16:04 -0800
commit12a26c298d2a8b1cab498533fa65198e49e3afd3 (patch)
tree131818a7e5b13dbb5d8556017ff06354415d097e /drivers/gpu/drm/msm/dsi/pll
parent4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323 (diff)
clk: divider: fix incorrect usage of container_of
divider_recalc_rate() is an helper function used by clock divider of different types, so the structure containing the 'hw' pointer is not always a 'struct clk_divider' At the following line: > div = _get_div(table, val, flags, divider->width); in several cases, the value of 'divider->width' is garbage as the actual structure behind this memory is not a 'struct clk_divider' Fortunately, this width value is used by _get_val() only when CLK_DIVIDER_MAX_AT_ZERO flag is set. This has never been the case so far when the structure is not a 'struct clk_divider'. This is probably why we did not notice this bug before Fixes: afe76c8fd030 ("clk: allow a clk divider with max divisor when zero") Signed-off-by: Jerome Brunet <> Acked-by: Alexandre Belloni <> Acked-by: Sylvain Lemieux <> Signed-off-by: Stephen Boyd <>
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/pll')
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
index fe15aa64086f..71fe60e5f01f 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
@@ -698,7 +698,7 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
val &= div_mask(width);
return divider_recalc_rate(hw, parent_rate, val, NULL,
- postdiv->flags);
+ postdiv->flags, width);
static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,