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authorArchit Taneja <architt@codeaurora.org>2018-01-17 11:35:27 +0530
committerRob Clark <robdclark@gmail.com>2018-02-20 10:41:21 -0500
commitff73ff19406098f71ec7628b951e0765f1df8128 (patch)
tree453848b889f930350430d98cb518abc0d42ae796 /drivers/gpu/drm/msm/dsi/dsi_host.c
parent28e4309ab9c2bade2a93bd3b4c583be5ec440b84 (diff)
drm/msm/dsi: Populate the 10nm PHY funcs
Populate the PHY ops with the downstream driver as reference. There are a couple of TODOs which need to be resolved: - The PHY timings are all hardcoded for now. This needs to be replaced with automatic calculations once we get/understand them. - There are some lane configuration registers which use a new representation between physical and logical lane mappings. For now, we've hardcoced them to follow the default mapping (i.e logical 0 -> phy 0, logical 1 -> phy 1 etc). Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/dsi/dsi_host.c')
0 files changed, 0 insertions, 0 deletions