drm/msm: sync generated headers

We haven't sync'd for a while.. pull in updates to get definitions for
some fields in pkt7 payloads.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

1 files changed, 1085 insertions, 17 deletions

diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
index 14eb52f3e605..54e1b2aa57d5 100644
--- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h
+++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h
@@ -8,19 +8,21 @@ http://github.com/freedreno/envytools/
 git clone https://github.com/freedreno/envytools.git
 
 The rules-ng-ng source files this header was generated from are:
-- /home/robclark/src/envytools/rnndb/adreno.xml               (    501 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml  (   1572 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml          (  42463 bytes, from 2018-11-19 13:44:03)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml (  14201 bytes, from 2018-12-02 17:29:54)
-- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml    (  43052 bytes, from 2018-12-02 17:29:54)
-- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml          (  83840 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml          ( 112086 bytes, from 2018-07-03 19:37:13)
-- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml          ( 147240 bytes, from 2018-12-02 17:29:54)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml          ( 140790 bytes, from 2018-12-02 17:29:54)
-- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml      (  10431 bytes, from 2018-09-14 13:03:07)
-- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2018-07-03 19:37:13)
-
-Copyright (C) 2013-2018 by the following authors:
+- /home/robclark/src/envytools/rnndb/adreno.xml                     (    594 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml        (   1572 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml                (  90159 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml       (  14386 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml          (  65048 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml                (  84226 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml                ( 112556 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml                ( 149461 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml                ( 184695 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml            (  11218 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml               (   1773 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml (   4559 bytes, from 2020-07-23 21:58:14)
+- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml    (   2872 bytes, from 2020-07-23 21:58:14)
+
+Copyright (C) 2013-2020 by the following authors:
 - Rob Clark <robdclark@gmail.com> (robclark)
 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
 
@@ -210,6 +212,854 @@ enum a2xx_rb_blend_opcode {
 	BLEND2_DST_PLUS_SRC_BIAS = 5,
 };
 
+enum a2xx_su_perfcnt_select {
+	PERF_PAPC_PASX_REQ = 0,
+	PERF_PAPC_PASX_FIRST_VECTOR = 2,
+	PERF_PAPC_PASX_SECOND_VECTOR = 3,
+	PERF_PAPC_PASX_FIRST_DEAD = 4,
+	PERF_PAPC_PASX_SECOND_DEAD = 5,
+	PERF_PAPC_PASX_VTX_KILL_DISCARD = 6,
+	PERF_PAPC_PASX_VTX_NAN_DISCARD = 7,
+	PERF_PAPC_PA_INPUT_PRIM = 8,
+	PERF_PAPC_PA_INPUT_NULL_PRIM = 9,
+	PERF_PAPC_PA_INPUT_EVENT_FLAG = 10,
+	PERF_PAPC_PA_INPUT_FIRST_PRIM_SLOT = 11,
+	PERF_PAPC_PA_INPUT_END_OF_PACKET = 12,
+	PERF_PAPC_CLPR_CULL_PRIM = 13,
+	PERF_PAPC_CLPR_VV_CULL_PRIM = 15,
+	PERF_PAPC_CLPR_VTX_KILL_CULL_PRIM = 17,
+	PERF_PAPC_CLPR_VTX_NAN_CULL_PRIM = 18,
+	PERF_PAPC_CLPR_CULL_TO_NULL_PRIM = 19,
+	PERF_PAPC_CLPR_VV_CLIP_PRIM = 21,
+	PERF_PAPC_CLPR_POINT_CLIP_CANDIDATE = 23,
+	PERF_PAPC_CLPR_CLIP_PLANE_CNT_1 = 24,
+	PERF_PAPC_CLPR_CLIP_PLANE_CNT_2 = 25,
+	PERF_PAPC_CLPR_CLIP_PLANE_CNT_3 = 26,
+	PERF_PAPC_CLPR_CLIP_PLANE_CNT_4 = 27,
+	PERF_PAPC_CLPR_CLIP_PLANE_CNT_5 = 28,
+	PERF_PAPC_CLPR_CLIP_PLANE_CNT_6 = 29,
+	PERF_PAPC_CLPR_CLIP_PLANE_NEAR = 30,
+	PERF_PAPC_CLPR_CLIP_PLANE_FAR = 31,
+	PERF_PAPC_CLPR_CLIP_PLANE_LEFT = 32,
+	PERF_PAPC_CLPR_CLIP_PLANE_RIGHT = 33,
+	PERF_PAPC_CLPR_CLIP_PLANE_TOP = 34,
+	PERF_PAPC_CLPR_CLIP_PLANE_BOTTOM = 35,
+	PERF_PAPC_CLSM_NULL_PRIM = 36,
+	PERF_PAPC_CLSM_TOTALLY_VISIBLE_PRIM = 37,
+	PERF_PAPC_CLSM_CLIP_PRIM = 38,
+	PERF_PAPC_CLSM_CULL_TO_NULL_PRIM = 39,
+	PERF_PAPC_CLSM_OUT_PRIM_CNT_1 = 40,
+	PERF_PAPC_CLSM_OUT_PRIM_CNT_2 = 41,
+	PERF_PAPC_CLSM_OUT_PRIM_CNT_3 = 42,
+	PERF_PAPC_CLSM_OUT_PRIM_CNT_4 = 43,
+	PERF_PAPC_CLSM_OUT_PRIM_CNT_5 = 44,
+	PERF_PAPC_CLSM_OUT_PRIM_CNT_6_7 = 45,
+	PERF_PAPC_CLSM_NON_TRIVIAL_CULL = 46,
+	PERF_PAPC_SU_INPUT_PRIM = 47,
+	PERF_PAPC_SU_INPUT_CLIP_PRIM = 48,
+	PERF_PAPC_SU_INPUT_NULL_PRIM = 49,
+	PERF_PAPC_SU_ZERO_AREA_CULL_PRIM = 50,
+	PERF_PAPC_SU_BACK_FACE_CULL_PRIM = 51,
+	PERF_PAPC_SU_FRONT_FACE_CULL_PRIM = 52,
+	PERF_PAPC_SU_POLYMODE_FACE_CULL = 53,
+	PERF_PAPC_SU_POLYMODE_BACK_CULL = 54,
+	PERF_PAPC_SU_POLYMODE_FRONT_CULL = 55,
+	PERF_PAPC_SU_POLYMODE_INVALID_FILL = 56,
+	PERF_PAPC_SU_OUTPUT_PRIM = 57,
+	PERF_PAPC_SU_OUTPUT_CLIP_PRIM = 58,
+	PERF_PAPC_SU_OUTPUT_NULL_PRIM = 59,
+	PERF_PAPC_SU_OUTPUT_EVENT_FLAG = 60,
+	PERF_PAPC_SU_OUTPUT_FIRST_PRIM_SLOT = 61,
+	PERF_PAPC_SU_OUTPUT_END_OF_PACKET = 62,
+	PERF_PAPC_SU_OUTPUT_POLYMODE_FACE = 63,
+	PERF_PAPC_SU_OUTPUT_POLYMODE_BACK = 64,
+	PERF_PAPC_SU_OUTPUT_POLYMODE_FRONT = 65,
+	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FACE = 66,
+	PERF_PAPC_SU_OUT_CLIP_POLYMODE_BACK = 67,
+	PERF_PAPC_SU_OUT_CLIP_POLYMODE_FRONT = 68,
+	PERF_PAPC_PASX_REQ_IDLE = 69,
+	PERF_PAPC_PASX_REQ_BUSY = 70,
+	PERF_PAPC_PASX_REQ_STALLED = 71,
+	PERF_PAPC_PASX_REC_IDLE = 72,
+	PERF_PAPC_PASX_REC_BUSY = 73,
+	PERF_PAPC_PASX_REC_STARVED_SX = 74,
+	PERF_PAPC_PASX_REC_STALLED = 75,
+	PERF_PAPC_PASX_REC_STALLED_POS_MEM = 76,
+	PERF_PAPC_PASX_REC_STALLED_CCGSM_IN = 77,
+	PERF_PAPC_CCGSM_IDLE = 78,
+	PERF_PAPC_CCGSM_BUSY = 79,
+	PERF_PAPC_CCGSM_STALLED = 80,
+	PERF_PAPC_CLPRIM_IDLE = 81,
+	PERF_PAPC_CLPRIM_BUSY = 82,
+	PERF_PAPC_CLPRIM_STALLED = 83,
+	PERF_PAPC_CLPRIM_STARVED_CCGSM = 84,
+	PERF_PAPC_CLIPSM_IDLE = 85,
+	PERF_PAPC_CLIPSM_BUSY = 86,
+	PERF_PAPC_CLIPSM_WAIT_CLIP_VERT_ENGH = 87,
+	PERF_PAPC_CLIPSM_WAIT_HIGH_PRI_SEQ = 88,
+	PERF_PAPC_CLIPSM_WAIT_CLIPGA = 89,
+	PERF_PAPC_CLIPSM_WAIT_AVAIL_VTE_CLIP = 90,
+	PERF_PAPC_CLIPSM_WAIT_CLIP_OUTSM = 91,
+	PERF_PAPC_CLIPGA_IDLE = 92,
+	PERF_PAPC_CLIPGA_BUSY = 93,
+	PERF_PAPC_CLIPGA_STARVED_VTE_CLIP = 94,
+	PERF_PAPC_CLIPGA_STALLED = 95,
+	PERF_PAPC_CLIP_IDLE = 96,
+	PERF_PAPC_CLIP_BUSY = 97,
+	PERF_PAPC_SU_IDLE = 98,
+	PERF_PAPC_SU_BUSY = 99,
+	PERF_PAPC_SU_STARVED_CLIP = 100,
+	PERF_PAPC_SU_STALLED_SC = 101,
+	PERF_PAPC_SU_FACENESS_CULL = 102,
+};
+
+enum a2xx_sc_perfcnt_select {
+	SC_SR_WINDOW_VALID = 0,
+	SC_CW_WINDOW_VALID = 1,
+	SC_QM_WINDOW_VALID = 2,
+	SC_FW_WINDOW_VALID = 3,
+	SC_EZ_WINDOW_VALID = 4,
+	SC_IT_WINDOW_VALID = 5,
+	SC_STARVED_BY_PA = 6,
+	SC_STALLED_BY_RB_TILE = 7,
+	SC_STALLED_BY_RB_SAMP = 8,
+	SC_STARVED_BY_RB_EZ = 9,
+	SC_STALLED_BY_SAMPLE_FF = 10,
+	SC_STALLED_BY_SQ = 11,
+	SC_STALLED_BY_SP = 12,
+	SC_TOTAL_NO_PRIMS = 13,
+	SC_NON_EMPTY_PRIMS = 14,
+	SC_NO_TILES_PASSING_QM = 15,
+	SC_NO_PIXELS_PRE_EZ = 16,
+	SC_NO_PIXELS_POST_EZ = 17,
+};
+
+enum a2xx_vgt_perfcount_select {
+	VGT_SQ_EVENT_WINDOW_ACTIVE = 0,
+	VGT_SQ_SEND = 1,
+	VGT_SQ_STALLED = 2,
+	VGT_SQ_STARVED_BUSY = 3,
+	VGT_SQ_STARVED_IDLE = 4,
+	VGT_SQ_STATIC = 5,
+	VGT_PA_EVENT_WINDOW_ACTIVE = 6,
+	VGT_PA_CLIP_V_SEND = 7,
+	VGT_PA_CLIP_V_STALLED = 8,
+	VGT_PA_CLIP_V_STARVED_BUSY = 9,
+	VGT_PA_CLIP_V_STARVED_IDLE = 10,
+	VGT_PA_CLIP_V_STATIC = 11,
+	VGT_PA_CLIP_P_SEND = 12,
+	VGT_PA_CLIP_P_STALLED = 13,
+	VGT_PA_CLIP_P_STARVED_BUSY = 14,
+	VGT_PA_CLIP_P_STARVED_IDLE = 15,
+	VGT_PA_CLIP_P_STATIC = 16,
+	VGT_PA_CLIP_S_SEND = 17,
+	VGT_PA_CLIP_S_STALLED = 18,
+	VGT_PA_CLIP_S_STARVED_BUSY = 19,
+	VGT_PA_CLIP_S_STARVED_IDLE = 20,
+	VGT_PA_CLIP_S_STATIC = 21,
+	RBIU_FIFOS_EVENT_WINDOW_ACTIVE = 22,
+	RBIU_IMMED_DATA_FIFO_STARVED = 23,
+	RBIU_IMMED_DATA_FIFO_STALLED = 24,
+	RBIU_DMA_REQUEST_FIFO_STARVED = 25,
+	RBIU_DMA_REQUEST_FIFO_STALLED = 26,
+	RBIU_DRAW_INITIATOR_FIFO_STARVED = 27,
+	RBIU_DRAW_INITIATOR_FIFO_STALLED = 28,
+	BIN_PRIM_NEAR_CULL = 29,
+	BIN_PRIM_ZERO_CULL = 30,
+	BIN_PRIM_FAR_CULL = 31,
+	BIN_PRIM_BIN_CULL = 32,
+	BIN_PRIM_FACE_CULL = 33,
+	SPARE34 = 34,
+	SPARE35 = 35,
+	SPARE36 = 36,
+	SPARE37 = 37,
+	SPARE38 = 38,
+	SPARE39 = 39,
+	TE_SU_IN_VALID = 40,
+	TE_SU_IN_READ = 41,
+	TE_SU_IN_PRIM = 42,
+	TE_SU_IN_EOP = 43,
+	TE_SU_IN_NULL_PRIM = 44,
+	TE_WK_IN_VALID = 45,
+	TE_WK_IN_READ = 46,
+	TE_OUT_PRIM_VALID = 47,
+	TE_OUT_PRIM_READ = 48,
+};
+
+enum a2xx_tcr_perfcount_select {
+	DGMMPD_IPMUX0_STALL = 0,
+	DGMMPD_IPMUX_ALL_STALL = 4,
+	OPMUX0_L2_WRITES = 5,
+};
+
+enum a2xx_tp_perfcount_select {
+	POINT_QUADS = 0,
+	BILIN_QUADS = 1,
+	ANISO_QUADS = 2,
+	MIP_QUADS = 3,
+	VOL_QUADS = 4,
+	MIP_VOL_QUADS = 5,
+	MIP_ANISO_QUADS = 6,
+	VOL_ANISO_QUADS = 7,
+	ANISO_2_1_QUADS = 8,
+	ANISO_4_1_QUADS = 9,
+	ANISO_6_1_QUADS = 10,
+	ANISO_8_1_QUADS = 11,
+	ANISO_10_1_QUADS = 12,
+	ANISO_12_1_QUADS = 13,
+	ANISO_14_1_QUADS = 14,
+	ANISO_16_1_QUADS = 15,
+	MIP_VOL_ANISO_QUADS = 16,
+	ALIGN_2_QUADS = 17,
+	ALIGN_4_QUADS = 18,
+	PIX_0_QUAD = 19,
+	PIX_1_QUAD = 20,
+	PIX_2_QUAD = 21,
+	PIX_3_QUAD = 22,
+	PIX_4_QUAD = 23,
+	TP_MIPMAP_LOD0 = 24,
+	TP_MIPMAP_LOD1 = 25,
+	TP_MIPMAP_LOD2 = 26,
+	TP_MIPMAP_LOD3 = 27,
+	TP_MIPMAP_LOD4 = 28,
+	TP_MIPMAP_LOD5 = 29,
+	TP_MIPMAP_LOD6 = 30,
+	TP_MIPMAP_LOD7 = 31,
+	TP_MIPMAP_LOD8 = 32,
+	TP_MIPMAP_LOD9 = 33,
+	TP_MIPMAP_LOD10 = 34,
+	TP_MIPMAP_LOD11 = 35,
+	TP_MIPMAP_LOD12 = 36,
+	TP_MIPMAP_LOD13 = 37,
+	TP_MIPMAP_LOD14 = 38,
+};
+
+enum a2xx_tcm_perfcount_select {
+	QUAD0_RD_LAT_FIFO_EMPTY = 0,
+	QUAD0_RD_LAT_FIFO_4TH_FULL = 3,
+	QUAD0_RD_LAT_FIFO_HALF_FULL = 4,
+	QUAD0_RD_LAT_FIFO_FULL = 5,
+	QUAD0_RD_LAT_FIFO_LT_4TH_FULL = 6,
+	READ_STARVED_QUAD0 = 28,
+	READ_STARVED = 32,
+	READ_STALLED_QUAD0 = 33,
+	READ_STALLED = 37,
+	VALID_READ_QUAD0 = 38,
+	TC_TP_STARVED_QUAD0 = 42,
+	TC_TP_STARVED = 46,
+};
+
+enum a2xx_tcf_perfcount_select {
+	VALID_CYCLES = 0,
+	SINGLE_PHASES = 1,
+	ANISO_PHASES = 2,
+	MIP_PHASES = 3,
+	VOL_PHASES = 4,
+	MIP_VOL_PHASES = 5,
+	MIP_ANISO_PHASES = 6,
+	VOL_ANISO_PHASES = 7,
+	ANISO_2_1_PHASES = 8,
+	ANISO_4_1_PHASES = 9,
+	ANISO_6_1_PHASES = 10,
+	ANISO_8_1_PHASES = 11,
+	ANISO_10_1_PHASES = 12,
+	ANISO_12_1_PHASES = 13,
+	ANISO_14_1_PHASES = 14,
+	ANISO_16_1_PHASES = 15,
+	MIP_VOL_ANISO_PHASES = 16,
+	ALIGN_2_PHASES = 17,
+	ALIGN_4_PHASES = 18,
+	TPC_BUSY = 19,
+	TPC_STALLED = 20,
+	TPC_STARVED = 21,
+	TPC_WORKING = 22,
+	TPC_WALKER_BUSY = 23,
+	TPC_WALKER_STALLED = 24,
+	TPC_WALKER_WORKING = 25,
+	TPC_ALIGNER_BUSY = 26,
+	TPC_ALIGNER_STALLED = 27,
+	TPC_ALIGNER_STALLED_BY_BLEND = 28,
+	TPC_ALIGNER_STALLED_BY_CACHE = 29,
+	TPC_ALIGNER_WORKING = 30,
+	TPC_BLEND_BUSY = 31,
+	TPC_BLEND_SYNC = 32,
+	TPC_BLEND_STARVED = 33,
+	TPC_BLEND_WORKING = 34,
+	OPCODE_0x00 = 35,
+	OPCODE_0x01 = 36,
+	OPCODE_0x04 = 37,
+	OPCODE_0x10 = 38,
+	OPCODE_0x11 = 39,
+	OPCODE_0x12 = 40,
+	OPCODE_0x13 = 41,
+	OPCODE_0x18 = 42,
+	OPCODE_0x19 = 43,
+	OPCODE_0x1A = 44,
+	OPCODE_OTHER = 45,
+	IN_FIFO_0_EMPTY = 56,
+	IN_FIFO_0_LT_HALF_FULL = 57,
+	IN_FIFO_0_HALF_FULL = 58,
+	IN_FIFO_0_FULL = 59,
+	IN_FIFO_TPC_EMPTY = 72,
+	IN_FIFO_TPC_LT_HALF_FULL = 73,
+	IN_FIFO_TPC_HALF_FULL = 74,
+	IN_FIFO_TPC_FULL = 75,
+	TPC_TC_XFC = 76,
+	TPC_TC_STATE = 77,
+	TC_STALL = 78,
+	QUAD0_TAPS = 79,
+	QUADS = 83,
+	TCA_SYNC_STALL = 84,
+	TAG_STALL = 85,
+	TCB_SYNC_STALL = 88,
+	TCA_VALID = 89,
+	PROBES_VALID = 90,
+	MISS_STALL = 91,
+	FETCH_FIFO_STALL = 92,
+	TCO_STALL = 93,
+	ANY_STALL = 94,
+	TAG_MISSES = 95,
+	TAG_HITS = 96,
+	SUB_TAG_MISSES = 97,
+	SET0_INVALIDATES = 98,
+	SET1_INVALIDATES = 99,
+	SET2_INVALIDATES = 100,
+	SET3_INVALIDATES = 101,
+	SET0_TAG_MISSES = 102,
+	SET1_TAG_MISSES = 103,
+	SET2_TAG_MISSES = 104,
+	SET3_TAG_MISSES = 105,
+	SET0_TAG_HITS = 106,
+	SET1_TAG_HITS = 107,
+	SET2_TAG_HITS = 108,
+	SET3_TAG_HITS = 109,
+	SET0_SUB_TAG_MISSES = 110,
+	SET1_SUB_TAG_MISSES = 111,
+	SET2_SUB_TAG_MISSES = 112,
+	SET3_SUB_TAG_MISSES = 113,
+	SET0_EVICT1 = 114,
+	SET0_EVICT2 = 115,
+	SET0_EVICT3 = 116,
+	SET0_EVICT4 = 117,
+	SET0_EVICT5 = 118,
+	SET0_EVICT6 = 119,
+	SET0_EVICT7 = 120,
+	SET0_EVICT8 = 121,
+	SET1_EVICT1 = 130,
+	SET1_EVICT2 = 131,
+	SET1_EVICT3 = 132,
+	SET1_EVICT4 = 133,
+	SET1_EVICT5 = 134,
+	SET1_EVICT6 = 135,
+	SET1_EVICT7 = 136,
+	SET1_EVICT8 = 137,
+	SET2_EVICT1 = 146,
+	SET2_EVICT2 = 147,
+	SET2_EVICT3 = 148,
+	SET2_EVICT4 = 149,
+	SET2_EVICT5 = 150,
+	SET2_EVICT6 = 151,
+	SET2_EVICT7 = 152,
+	SET2_EVICT8 = 153,
+	SET3_EVICT1 = 162,
+	SET3_EVICT2 = 163,
+	SET3_EVICT3 = 164,
+	SET3_EVICT4 = 165,
+	SET3_EVICT5 = 166,
+	SET3_EVICT6 = 167,
+	SET3_EVICT7 = 168,
+	SET3_EVICT8 = 169,
+	FF_EMPTY = 178,
+	FF_LT_HALF_FULL = 179,
+	FF_HALF_FULL = 180,
+	FF_FULL = 181,
+	FF_XFC = 182,
+	FF_STALLED = 183,
+	FG_MASKS = 184,
+	FG_LEFT_MASKS = 185,
+	FG_LEFT_MASK_STALLED = 186,
+	FG_LEFT_NOT_DONE_STALL = 187,
+	FG_LEFT_FG_STALL = 188,
+	FG_LEFT_SECTORS = 189,
+	FG0_REQUESTS = 195,
+	FG0_STALLED = 196,
+	MEM_REQ512 = 199,
+	MEM_REQ_SENT = 200,
+	MEM_LOCAL_READ_REQ = 202,
+	TC0_MH_STALLED = 203,
+};
+
+enum a2xx_sq_perfcnt_select {
+	SQ_PIXEL_VECTORS_SUB = 0,
+	SQ_VERTEX_VECTORS_SUB = 1,
+	SQ_ALU0_ACTIVE_VTX_SIMD0 = 2,
+	SQ_ALU1_ACTIVE_VTX_SIMD0 = 3,
+	SQ_ALU0_ACTIVE_PIX_SIMD0 = 4,
+	SQ_ALU1_ACTIVE_PIX_SIMD0 = 5,
+	SQ_ALU0_ACTIVE_VTX_SIMD1 = 6,
+	SQ_ALU1_ACTIVE_VTX_SIMD1 = 7,
+	SQ_ALU0_ACTIVE_PIX_SIMD1 = 8,
+	SQ_ALU1_ACTIVE_PIX_SIMD1 = 9,
+	SQ_EXPORT_CYCLES = 10,
+	SQ_ALU_CST_WRITTEN = 11,
+	SQ_TEX_CST_WRITTEN = 12,
+	SQ_ALU_CST_STALL = 13,
+	SQ_ALU_TEX_STALL = 14,
+	SQ_INST_WRITTEN = 15,
+	SQ_BOOLEAN_WRITTEN = 16,
+	SQ_LOOPS_WRITTEN = 17,
+	SQ_PIXEL_SWAP_IN = 18,
+	SQ_PIXEL_SWAP_OUT = 19,
+	SQ_VERTEX_SWAP_IN = 20,
+	SQ_VERTEX_SWAP_OUT = 21,
+	SQ_ALU_VTX_INST_ISSUED = 22,
+	SQ_TEX_VTX_INST_ISSUED = 23,
+	SQ_VC_VTX_INST_ISSUED = 24,
+	SQ_CF_VTX_INST_ISSUED = 25,
+	SQ_ALU_PIX_INST_ISSUED = 26,
+	SQ_TEX_PIX_INST_ISSUED = 27,
+	SQ_VC_PIX_INST_ISSUED = 28,
+	SQ_CF_PIX_INST_ISSUED = 29,
+	SQ_ALU0_FIFO_EMPTY_SIMD0 = 30,
+	SQ_ALU1_FIFO_EMPTY_SIMD0 = 31,
+	SQ_ALU0_FIFO_EMPTY_SIMD1 = 32,
+	SQ_ALU1_FIFO_EMPTY_SIMD1 = 33,
+	SQ_ALU_NOPS = 34,
+	SQ_PRED_SKIP = 35,
+	SQ_SYNC_ALU_STALL_SIMD0_VTX = 36,
+	SQ_SYNC_ALU_STALL_SIMD1_VTX = 37,
+	SQ_SYNC_TEX_STALL_VTX = 38,
+	SQ_SYNC_VC_STALL_VTX = 39,
+	SQ_CONSTANTS_USED_SIMD0 = 40,
+	SQ_CONSTANTS_SENT_SP_SIMD0 = 41,
+	SQ_GPR_STALL_VTX = 42,
+	SQ_GPR_STALL_PIX = 43,
+	SQ_VTX_RS_STALL = 44,
+	SQ_PIX_RS_STALL = 45,
+	SQ_SX_PC_FULL = 46,
+	SQ_SX_EXP_BUFF_FULL = 47,
+	SQ_SX_POS_BUFF_FULL = 48,
+	SQ_INTERP_QUADS = 49,
+	SQ_INTERP_ACTIVE = 50,
+	SQ_IN_PIXEL_STALL = 51,
+	SQ_IN_VTX_STALL = 52,
+	SQ_VTX_CNT = 53,
+	SQ_VTX_VECTOR2 = 54,
+	SQ_VTX_VECTOR3 = 55,
+	SQ_VTX_VECTOR4 = 56,
+	SQ_PIXEL_VECTOR1 = 57,
+	SQ_PIXEL_VECTOR23 = 58,
+	SQ_PIXEL_VECTOR4 = 59,
+	SQ_CONSTANTS_USED_SIMD1 = 60,
+	SQ_CONSTANTS_SENT_SP_SIMD1 = 61,
+	SQ_SX_MEM_EXP_FULL = 62,
+	SQ_ALU0_ACTIVE_VTX_SIMD2 = 63,
+	SQ_ALU1_ACTIVE_VTX_SIMD2 = 64,
+	SQ_ALU0_ACTIVE_PIX_SIMD2 = 65,
+	SQ_ALU1_ACTIVE_PIX_SIMD2 = 66,
+	SQ_ALU0_ACTIVE_VTX_SIMD3 = 67,
+	SQ_PERFCOUNT_VTX_QUAL_TP_DONE = 68,
+	SQ_ALU0_ACTIVE_PIX_SIMD3 = 69,
+	SQ_PERFCOUNT_PIX_QUAL_TP_DONE = 70,
+	SQ_ALU0_FIFO_EMPTY_SIMD2 = 71,
+	SQ_ALU1_FIFO_EMPTY_SIMD2 = 72,
+	SQ_ALU0_FIFO_EMPTY_SIMD3 = 73,
+	SQ_ALU1_FIFO_EMPTY_SIMD3 = 74,
+	SQ_SYNC_ALU_STALL_SIMD2_VTX = 75,
+	SQ_PERFCOUNT_VTX_POP_THREAD = 76,
+	SQ_SYNC_ALU_STALL_SIMD0_PIX = 77,
+	SQ_SYNC_ALU_STALL_SIMD1_PIX = 78,
+	SQ_SYNC_ALU_STALL_SIMD2_PIX = 79,
+	SQ_PERFCOUNT_PIX_POP_THREAD = 80,
+	SQ_SYNC_TEX_STALL_PIX = 81,
+	SQ_SYNC_VC_STALL_PIX = 82,
+	SQ_CONSTANTS_USED_SIMD2 = 83,
+	SQ_CONSTANTS_SENT_SP_SIMD2 = 84,
+	SQ_PERFCOUNT_VTX_DEALLOC_ACK = 85,
+	SQ_PERFCOUNT_PIX_DEALLOC_ACK = 86,
+	SQ_ALU0_FIFO_FULL_SIMD0 = 87,
+	SQ_ALU1_FIFO_FULL_SIMD0 = 88,
+	SQ_ALU0_FIFO_FULL_SIMD1 = 89,
+	SQ_ALU1_FIFO_FULL_SIMD1 = 90,
+	SQ_ALU0_FIFO_FULL_SIMD2 = 91,
+	SQ_ALU1_FIFO_FULL_SIMD2 = 92,
+	SQ_ALU0_FIFO_FULL_SIMD3 = 93,
+	SQ_ALU1_FIFO_FULL_SIMD3 = 94,
+	VC_PERF_STATIC = 95,
+	VC_PERF_STALLED = 96,
+	VC_PERF_STARVED = 97,
+	VC_PERF_SEND = 98,
+	VC_PERF_ACTUAL_STARVED = 99,
+	PIXEL_THREAD_0_ACTIVE = 100,
+	VERTEX_THREAD_0_ACTIVE = 101,
+	PIXEL_THREAD_0_NUMBER = 102,
+	VERTEX_THREAD_0_NUMBER = 103,
+	VERTEX_EVENT_NUMBER = 104,
+	PIXEL_EVENT_NUMBER = 105,
+	PTRBUFF_EF_PUSH = 106,
+	PTRBUFF_EF_POP_EVENT = 107,
+	PTRBUFF_EF_POP_NEW_VTX = 108,
+	PTRBUFF_EF_POP_DEALLOC = 109,
+	PTRBUFF_EF_POP_PVECTOR = 110,
+	PTRBUFF_EF_POP_PVECTOR_X = 111,
+	PTRBUFF_EF_POP_PVECTOR_VNZ = 112,
+	PTRBUFF_PB_DEALLOC = 113,
+	PTRBUFF_PI_STATE_PPB_POP = 114,
+	PTRBUFF_PI_RTR = 115,
+	PTRBUFF_PI_READ_EN = 116,
+	PTRBUFF_PI_BUFF_SWAP = 117,
+	PTRBUFF_SQ_FREE_BUFF = 118,
+	PTRBUFF_SQ_DEC = 119,
+	PTRBUFF_SC_VALID_CNTL_EVENT = 120,
+	PTRBUFF_SC_VALID_IJ_XFER = 121,
+	PTRBUFF_SC_NEW_VECTOR_1_Q = 122,
+	PTRBUFF_QUAL_NEW_VECTOR = 123,
+	PTRBUFF_QUAL_EVENT = 124,
+	PTRBUFF_END_BUFFER = 125,
+	PTRBUFF_FILL_QUAD = 126,
+	VERTS_WRITTEN_SPI = 127,
+	TP_FETCH_INSTR_EXEC = 128,
+	TP_FETCH_INSTR_REQ = 129,
+	TP_DATA_RETURN = 130,
+	SPI_WRITE_CYCLES_SP = 131,
+	SPI_WRITES_SP = 132,
+	SP_ALU_INSTR_EXEC = 133,
+	SP_CONST_ADDR_TO_SQ = 134,
+	SP_PRED_KILLS_TO_SQ = 135,
+	SP_EXPORT_CYCLES_TO_SX = 136,
+	SP_EXPORTS_TO_SX = 137,
+	SQ_CYCLES_ELAPSED = 138,
+	SQ_TCFS_OPT_ALLOC_EXEC = 139,
+	SQ_TCFS_NO_OPT_ALLOC = 140,
+	SQ_ALU0_NO_OPT_ALLOC = 141,
+	SQ_ALU1_NO_OPT_ALLOC = 142,
+	SQ_TCFS_ARB_XFC_CNT = 143,
+	SQ_ALU0_ARB_XFC_CNT = 144,
+	SQ_ALU1_ARB_XFC_CNT = 145,
+	SQ_TCFS_CFS_UPDATE_CNT = 146,
+	SQ_ALU0_CFS_UPDATE_CNT = 147,
+	SQ_ALU1_CFS_UPDATE_CNT = 148,
+	SQ_VTX_PUSH_THREAD_CNT = 149,
+	SQ_VTX_POP_THREAD_CNT = 150,
+	SQ_PIX_PUSH_THREAD_CNT = 151,
+	SQ_PIX_POP_THREAD_CNT = 152,
+	SQ_PIX_TOTAL = 153,
+	SQ_PIX_KILLED = 154,
+};
+
+enum a2xx_sx_perfcnt_select {
+	SX_EXPORT_VECTORS = 0,
+	SX_DUMMY_QUADS = 1,
+	SX_ALPHA_FAIL = 2,
+	SX_RB_QUAD_BUSY = 3,
+	SX_RB_COLOR_BUSY = 4,
+	SX_RB_QUAD_STALL = 5,
+	SX_RB_COLOR_STALL = 6,
+};
+
+enum a2xx_rbbm_perfcount1_sel {
+	RBBM1_COUNT = 0,
+	RBBM1_NRT_BUSY = 1,
+	RBBM1_RB_BUSY = 2,
+	RBBM1_SQ_CNTX0_BUSY = 3,
+	RBBM1_SQ_CNTX17_BUSY = 4,
+	RBBM1_VGT_BUSY = 5,
+	RBBM1_VGT_NODMA_BUSY = 6,
+	RBBM1_PA_BUSY = 7,
+	RBBM1_SC_CNTX_BUSY = 8,
+	RBBM1_TPC_BUSY = 9,
+	RBBM1_TC_BUSY = 10,
+	RBBM1_SX_BUSY = 11,
+	RBBM1_CP_COHER_BUSY = 12,
+	RBBM1_CP_NRT_BUSY = 13,
+	RBBM1_GFX_IDLE_STALL = 14,
+	RBBM1_INTERRUPT = 15,
+};
+
+enum a2xx_cp_perfcount_sel {
+	ALWAYS_COUNT = 0,
+	TRANS_FIFO_FULL = 1,
+	TRANS_FIFO_AF = 2,
+	RCIU_PFPTRANS_WAIT = 3,
+	RCIU_NRTTRANS_WAIT = 6,
+	CSF_NRT_READ_WAIT = 8,
+	CSF_I1_FIFO_FULL = 9,
+	CSF_I2_FIFO_FULL = 10,
+	CSF_ST_FIFO_FULL = 11,
+	CSF_RING_ROQ_FULL = 13,
+	CSF_I1_ROQ_FULL = 14,
+	CSF_I2_ROQ_FULL = 15,
+	CSF_ST_ROQ_FULL = 16,
+	MIU_TAG_MEM_FULL = 18,
+	MIU_WRITECLEAN = 19,
+	MIU_NRT_WRITE_STALLED = 22,
+	MIU_NRT_READ_STALLED = 23,
+	ME_WRITE_CONFIRM_FIFO_FULL = 24,
+	ME_VS_DEALLOC_FIFO_FULL = 25,
+	ME_PS_DEALLOC_FIFO_FULL = 26,
+	ME_REGS_VS_EVENT_FIFO_FULL = 27,
+	ME_REGS_PS_EVENT_FIFO_FULL = 28,
+	ME_REGS_CF_EVENT_FIFO_FULL = 29,
+	ME_MICRO_RB_STARVED = 30,
+	ME_MICRO_I1_STARVED = 31,
+	ME_MICRO_I2_STARVED = 32,
+	ME_MICRO_ST_STARVED = 33,
+	RCIU_RBBM_DWORD_SENT = 40,
+	ME_BUSY_CLOCKS = 41,
+	ME_WAIT_CONTEXT_AVAIL = 42,
+	PFP_TYPE0_PACKET = 43,
+	PFP_TYPE3_PACKET = 44,
+	CSF_RB_WPTR_NEQ_RPTR = 45,
+	CSF_I1_SIZE_NEQ_ZERO = 46,
+	CSF_I2_SIZE_NEQ_ZERO = 47,
+	CSF_RBI1I2_FETCHING = 48,
+};
+
+enum a2xx_rb_perfcnt_select {
+	RBPERF_CNTX_BUSY = 0,
+	RBPERF_CNTX_BUSY_MAX = 1,
+	RBPERF_SX_QUAD_STARVED = 2,
+	RBPERF_SX_QUAD_STARVED_MAX = 3,
+	RBPERF_GA_GC_CH0_SYS_REQ = 4,
+	RBPERF_GA_GC_CH0_SYS_REQ_MAX = 5,
+	RBPERF_GA_GC_CH1_SYS_REQ = 6,
+	RBPERF_GA_GC_CH1_SYS_REQ_MAX = 7,
+	RBPERF_MH_STARVED = 8,
+	RBPERF_MH_STARVED_MAX = 9,
+	RBPERF_AZ_BC_COLOR_BUSY = 10,
+	RBPERF_AZ_BC_COLOR_BUSY_MAX = 11,
+	RBPERF_AZ_BC_Z_BUSY = 12,
+	RBPERF_AZ_BC_Z_BUSY_MAX = 13,
+	RBPERF_RB_SC_TILE_RTR_N = 14,
+	RBPERF_RB_SC_TILE_RTR_N_MAX = 15,
+	RBPERF_RB_SC_SAMP_RTR_N = 16,
+	RBPERF_RB_SC_SAMP_RTR_N_MAX = 17,
+	RBPERF_RB_SX_QUAD_RTR_N = 18,
+	RBPERF_RB_SX_QUAD_RTR_N_MAX = 19,
+	RBPERF_RB_SX_COLOR_RTR_N = 20,
+	RBPERF_RB_SX_COLOR_RTR_N_MAX = 21,
+	RBPERF_RB_SC_SAMP_LZ_BUSY = 22,
+	RBPERF_RB_SC_SAMP_LZ_BUSY_MAX = 23,
+	RBPERF_ZXP_STALL = 24,
+	RBPERF_ZXP_STALL_MAX = 25,
+	RBPERF_EVENT_PENDING = 26,
+	RBPERF_EVENT_PENDING_MAX = 27,
+	RBPERF_RB_MH_VALID = 28,
+	RBPERF_RB_MH_VALID_MAX = 29,
+	RBPERF_SX_RB_QUAD_SEND = 30,
+	RBPERF_SX_RB_COLOR_SEND = 31,
+	RBPERF_SC_RB_TILE_SEND = 32,
+	RBPERF_SC_RB_SAMPLE_SEND = 33,
+	RBPERF_SX_RB_MEM_EXPORT = 34,
+	RBPERF_SX_RB_QUAD_EVENT = 35,
+	RBPERF_SC_RB_TILE_EVENT_FILTERED = 36,
+	RBPERF_SC_RB_TILE_EVENT_ALL = 37,
+	RBPERF_RB_SC_EZ_SEND = 38,
+	RBPERF_RB_SX_INDEX_SEND = 39,
+	RBPERF_GMEM_INTFO_RD = 40,
+	RBPERF_GMEM_INTF1_RD = 41,
+	RBPERF_GMEM_INTFO_WR = 42,
+	RBPERF_GMEM_INTF1_WR = 43,
+	RBPERF_RB_CP_CONTEXT_DONE = 44,
+	RBPERF_RB_CP_CACHE_FLUSH = 45,
+	RBPERF_ZPASS_DONE = 46,
+	RBPERF_ZCMD_VALID = 47,
+	RBPERF_CCMD_VALID = 48,
+	RBPERF_ACCUM_GRANT = 49,
+	RBPERF_ACCUM_C0_GRANT = 50,
+	RBPERF_ACCUM_C1_GRANT = 51,
+	RBPERF_ACCUM_FULL_BE_WR = 52,
+	RBPERF_ACCUM_REQUEST_NO_GRANT = 53,
+	RBPERF_ACCUM_TIMEOUT_PULSE = 54,
+	RBPERF_ACCUM_LIN_TIMEOUT_PULSE = 55,
+	RBPERF_ACCUM_CAM_HIT_FLUSHING = 56,
+};
+
+enum a2xx_mh_perfcnt_select {
+	CP_R0_REQUESTS = 0,
+	CP_R1_REQUESTS = 1,
+	CP_R2_REQUESTS = 2,
+	CP_R3_REQUESTS = 3,
+	CP_R4_REQUESTS = 4,
+	CP_TOTAL_READ_REQUESTS = 5,
+	CP_TOTAL_WRITE_REQUESTS = 6,
+	CP_TOTAL_REQUESTS = 7,
+	CP_DATA_BYTES_WRITTEN = 8,
+	CP_WRITE_CLEAN_RESPONSES = 9,
+	CP_R0_READ_BURSTS_RECEIVED = 10,
+	CP_R1_READ_BURSTS_RECEIVED = 11,
+	CP_R2_READ_BURSTS_RECEIVED = 12,
+	CP_R3_READ_BURSTS_RECEIVED = 13,
+	CP_R4_READ_BURSTS_RECEIVED = 14,
+	CP_TOTAL_READ_BURSTS_RECEIVED = 15,
+	CP_R0_DATA_BEATS_READ = 16,
+	CP_R1_DATA_BEATS_READ = 17,
+	CP_R2_DATA_BEATS_READ = 18,
+	CP_R3_DATA_BEATS_READ = 19,
+	CP_R4_DATA_BEATS_READ = 20,
+	CP_TOTAL_DATA_BEATS_READ = 21,
+	VGT_R0_REQUESTS = 22,
+	VGT_R1_REQUESTS = 23,
+	VGT_TOTAL_REQUESTS = 24,
+	VGT_R0_READ_BURSTS_RECEIVED = 25,
+	VGT_R1_READ_BURSTS_RECEIVED = 26,
+	VGT_TOTAL_READ_BURSTS_RECEIVED = 27,
+	VGT_R0_DATA_BEATS_READ = 28,
+	VGT_R1_DATA_BEATS_READ = 29,
+	VGT_TOTAL_DATA_BEATS_READ = 30,
+	TC_TOTAL_REQUESTS = 31,
+	TC_ROQ_REQUESTS = 32,
+	TC_INFO_SENT = 33,
+	TC_READ_BURSTS_RECEIVED = 34,
+	TC_DATA_BEATS_READ = 35,
+	TCD_BURSTS_READ = 36,
+	RB_REQUESTS = 37,
+	RB_DATA_BYTES_WRITTEN = 38,
+	RB_WRITE_CLEAN_RESPONSES = 39,
+	AXI_READ_REQUESTS_ID_0 = 40,
+	AXI_READ_REQUESTS_ID_1 = 41,
+	AXI_READ_REQUESTS_ID_2 = 42,
+	AXI_READ_REQUESTS_ID_3 = 43,
+	AXI_READ_REQUESTS_ID_4 = 44,
+	AXI_READ_REQUESTS_ID_5 = 45,
+	AXI_READ_REQUESTS_ID_6 = 46,
+	AXI_READ_REQUESTS_ID_7 = 47,
+	AXI_TOTAL_READ_REQUESTS = 48,
+	AXI_WRITE_REQUESTS_ID_0 = 49,
+	AXI_WRITE_REQUESTS_ID_1 = 50,
+	AXI_WRITE_REQUESTS_ID_2 = 51,
+	AXI_WRITE_REQUESTS_ID_3 = 52,
+	AXI_WRITE_REQUESTS_ID_4 = 53,
+	AXI_WRITE_REQUESTS_ID_5 = 54,
+	AXI_WRITE_REQUESTS_ID_6 = 55,
+	AXI_WRITE_REQUESTS_ID_7 = 56,
+	AXI_TOTAL_WRITE_REQUESTS = 57,
+	AXI_TOTAL_REQUESTS_ID_0 = 58,
+	AXI_TOTAL_REQUESTS_ID_1 = 59,
+	AXI_TOTAL_REQUESTS_ID_2 = 60,
+	AXI_TOTAL_REQUESTS_ID_3 = 61,
+	AXI_TOTAL_REQUESTS_ID_4 = 62,
+	AXI_TOTAL_REQUESTS_ID_5 = 63,
+	AXI_TOTAL_REQUESTS_ID_6 = 64,
+	AXI_TOTAL_REQUESTS_ID_7 = 65,
+	AXI_TOTAL_REQUESTS = 66,
+	AXI_READ_CHANNEL_BURSTS_ID_0 = 67,
+	AXI_READ_CHANNEL_BURSTS_ID_1 = 68,
+	AXI_READ_CHANNEL_BURSTS_ID_2 = 69,
+	AXI_READ_CHANNEL_BURSTS_ID_3 = 70,
+	AXI_READ_CHANNEL_BURSTS_ID_4 = 71,
+	AXI_READ_CHANNEL_BURSTS_ID_5 = 72,
+	AXI_READ_CHANNEL_BURSTS_ID_6 = 73,
+	AXI_READ_CHANNEL_BURSTS_ID_7 = 74,
+	AXI_READ_CHANNEL_TOTAL_BURSTS = 75,
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_0 = 76,
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_1 = 77,
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_2 = 78,
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_3 = 79,
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_4 = 80,
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_5 = 81,
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_6 = 82,
+	AXI_READ_CHANNEL_DATA_BEATS_READ_ID_7 = 83,
+	AXI_READ_CHANNEL_TOTAL_DATA_BEATS_READ = 84,
+	AXI_WRITE_CHANNEL_BURSTS_ID_0 = 85,
+	AXI_WRITE_CHANNEL_BURSTS_ID_1 = 86,
+	AXI_WRITE_CHANNEL_BURSTS_ID_2 = 87,
+	AXI_WRITE_CHANNEL_BURSTS_ID_3 = 88,
+	AXI_WRITE_CHANNEL_BURSTS_ID_4 = 89,
+	AXI_WRITE_CHANNEL_BURSTS_ID_5 = 90,
+	AXI_WRITE_CHANNEL_BURSTS_ID_6 = 91,
+	AXI_WRITE_CHANNEL_BURSTS_ID_7 = 92,
+	AXI_WRITE_CHANNEL_TOTAL_BURSTS = 93,
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_0 = 94,
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_1 = 95,
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_2 = 96,
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_3 = 97,
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_4 = 98,
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_5 = 99,
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_6 = 100,
+	AXI_WRITE_CHANNEL_DATA_BYTES_WRITTEN_ID_7 = 101,
+	AXI_WRITE_CHANNEL_TOTAL_DATA_BYTES_WRITTEN = 102,
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_0 = 103,
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_1 = 104,
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_2 = 105,
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_3 = 106,
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_4 = 107,
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_5 = 108,
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_6 = 109,
+	AXI_WRITE_RESPONSE_CHANNEL_RESPONSES_ID_7 = 110,
+	AXI_WRITE_RESPONSE_CHANNEL_TOTAL_RESPONSES = 111,
+	TOTAL_MMU_MISSES = 112,
+	MMU_READ_MISSES = 113,
+	MMU_WRITE_MISSES = 114,
+	TOTAL_MMU_HITS = 115,
+	MMU_READ_HITS = 116,
+	MMU_WRITE_HITS = 117,
+	SPLIT_MODE_TC_HITS = 118,
+	SPLIT_MODE_TC_MISSES = 119,
+	SPLIT_MODE_NON_TC_HITS = 120,
+	SPLIT_MODE_NON_TC_MISSES = 121,
+	STALL_AWAITING_TLB_MISS_FETCH = 122,
+	MMU_TLB_MISS_READ_BURSTS_RECEIVED = 123,
+	MMU_TLB_MISS_DATA_BEATS_READ = 124,
+	CP_CYCLES_HELD_OFF = 125,
+	VGT_CYCLES_HELD_OFF = 126,
+	TC_CYCLES_HELD_OFF = 127,
+	TC_ROQ_CYCLES_HELD_OFF = 128,
+	TC_CYCLES_HELD_OFF_TCD_FULL = 129,
+	RB_CYCLES_HELD_OFF = 130,
+	TOTAL_CYCLES_ANY_CLNT_HELD_OFF = 131,
+	TLB_MISS_CYCLES_HELD_OFF = 132,
+	AXI_READ_REQUEST_HELD_OFF = 133,
+	AXI_WRITE_REQUEST_HELD_OFF = 134,
+	AXI_REQUEST_HELD_OFF = 135,
+	AXI_REQUEST_HELD_OFF_INFLIGHT_LIMIT = 136,
+	AXI_WRITE_DATA_HELD_OFF = 137,
+	CP_SAME_PAGE_BANK_REQUESTS = 138,
+	VGT_SAME_PAGE_BANK_REQUESTS = 139,
+	TC_SAME_PAGE_BANK_REQUESTS = 140,
+	TC_ARB_HOLD_SAME_PAGE_BANK_REQUESTS = 141,
+	RB_SAME_PAGE_BANK_REQUESTS = 142,
+	TOTAL_SAME_PAGE_BANK_REQUESTS = 143,
+	CP_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 144,
+	VGT_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 145,
+	TC_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 146,
+	RB_SAME_PAGE_BANK_REQUESTS_KILLED_FAIRNESS_LIMIT = 147,
+	TOTAL_SAME_PAGE_BANK_KILLED_FAIRNESS_LIMIT = 148,
+	TOTAL_MH_READ_REQUESTS = 149,
+	TOTAL_MH_WRITE_REQUESTS = 150,
+	TOTAL_MH_REQUESTS = 151,
+	MH_BUSY = 152,
+	CP_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 153,
+	VGT_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 154,
+	TC_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 155,
+	RB_NTH_ACCESS_SAME_PAGE_BANK_SEQUENCE = 156,
+	TC_ROQ_N_VALID_ENTRIES = 157,
+	ARQ_N_ENTRIES = 158,
+	WDB_N_ENTRIES = 159,
+	MH_READ_LATENCY_OUTST_REQ_SUM = 160,
+	MC_READ_LATENCY_OUTST_REQ_SUM = 161,
+	MC_TOTAL_READ_REQUESTS = 162,
+	ELAPSED_CYCLES_MH_GATED_CLK = 163,
+	ELAPSED_CLK_CYCLES = 164,
+	CP_W_16B_REQUESTS = 165,
+	CP_W_32B_REQUESTS = 166,
+	TC_16B_REQUESTS = 167,
+	TC_32B_REQUESTS = 168,
+	PA_REQUESTS = 169,
+	PA_DATA_BYTES_WRITTEN = 170,
+	PA_WRITE_CLEAN_RESPONSES = 171,
+	PA_CYCLES_HELD_OFF = 172,
+	AXI_READ_REQUEST_DATA_BEATS_ID_0 = 173,
+	AXI_READ_REQUEST_DATA_BEATS_ID_1 = 174,
+	AXI_READ_REQUEST_DATA_BEATS_ID_2 = 175,
+	AXI_READ_REQUEST_DATA_BEATS_ID_3 = 176,
+	AXI_READ_REQUEST_DATA_BEATS_ID_4 = 177,
+	AXI_READ_REQUEST_DATA_BEATS_ID_5 = 178,
+	AXI_READ_REQUEST_DATA_BEATS_ID_6 = 179,
+	AXI_READ_REQUEST_DATA_BEATS_ID_7 = 180,
+	AXI_TOTAL_READ_REQUEST_DATA_BEATS = 181,
+};
+
 enum adreno_mmu_clnt_beh {
 	BEH_NEVR = 0,
 	BEH_TRAN_RNG = 1,
@@ -268,9 +1118,9 @@ enum sq_tex_border_color {
 };
 
 enum sq_tex_sign {
-	SQ_TEX_SIGN_UNISIGNED = 0,
+	SQ_TEX_SIGN_UNSIGNED = 0,
 	SQ_TEX_SIGN_SIGNED = 1,
-	SQ_TEX_SIGN_UNISIGNED_BIASED = 2,
+	SQ_TEX_SIGN_UNSIGNED_BIASED = 2,
 	SQ_TEX_SIGN_GAMMA = 3,
 };
 
@@ -1842,6 +2692,10 @@ static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
 
 #define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_SCALE			0x00002380
 
+#define REG_A2XX_PA_SU_POLY_OFFSET_FRONT_OFFSET			0x00002381
+
+#define REG_A2XX_PA_SU_POLY_OFFSET_BACK_SCALE			0x00002382
+
 #define REG_A2XX_PA_SU_POLY_OFFSET_BACK_OFFSET			0x00002383
 
 #define REG_A2XX_SQ_CONSTANT_0					0x00004000
@@ -1858,6 +2712,220 @@ static inline uint32_t A2XX_RB_COPY_DEST_OFFSET_Y(uint32_t val)
 
 #define REG_A2XX_COHER_STATUS_PM4				0x00000a2b
 
+#define REG_A2XX_PA_SU_PERFCOUNTER0_SELECT			0x00000c88
+
+#define REG_A2XX_PA_SU_PERFCOUNTER1_SELECT			0x00000c89
+
+#define REG_A2XX_PA_SU_PERFCOUNTER2_SELECT			0x00000c8a
+
+#define REG_A2XX_PA_SU_PERFCOUNTER3_SELECT			0x00000c8b
+
+#define REG_A2XX_PA_SU_PERFCOUNTER0_LOW				0x00000c8c
+
+#define REG_A2XX_PA_SU_PERFCOUNTER0_HI				0x00000c8d
+
+#define REG_A2XX_PA_SU_PERFCOUNTER1_LOW				0x00000c8e
+
+#define REG_A2XX_PA_SU_PERFCOUNTER1_HI				0x00000c8f
+
+#define REG_A2XX_PA_SU_PERFCOUNTER2_LOW				0x00000c90
+
+#define REG_A2XX_PA_SU_PERFCOUNTER2_HI				0x00000c91
+
+#define REG_A2XX_PA_SU_PERFCOUNTER3_LOW				0x00000c92
+
+#define REG_A2XX_PA_SU_PERFCOUNTER3_HI				0x00000c93
+
+#define REG_A2XX_PA_SC_PERFCOUNTER0_SELECT			0x00000c98
+
+#define REG_A2XX_PA_SC_PERFCOUNTER0_LOW				0x00000c99
+
+#define REG_A2XX_PA_SC_PERFCOUNTER0_HI				0x00000c9a
+
+#define REG_A2XX_VGT_PERFCOUNTER0_SELECT			0x00000c48
+
+#define REG_A2XX_VGT_PERFCOUNTER1_SELECT			0x00000c49
+
+#define REG_A2XX_VGT_PERFCOUNTER2_SELECT			0x00000c4a
+
+#define REG_A2XX_VGT_PERFCOUNTER3_SELECT			0x00000c4b
+
+#define REG_A2XX_VGT_PERFCOUNTER0_LOW				0x00000c4c
+
+#define REG_A2XX_VGT_PERFCOUNTER1_LOW				0x00000c4e
+
+#define REG_A2XX_VGT_PERFCOUNTER2_LOW				0x00000c50
+
+#define REG_A2XX_VGT_PERFCOUNTER3_LOW				0x00000c52
+
+#define REG_A2XX_VGT_PERFCOUNTER0_HI				0x00000c4d
+
+#define REG_A2XX_VGT_PERFCOUNTER1_HI				0x00000c4f
+
+#define REG_A2XX_VGT_PERFCOUNTER2_HI				0x00000c51
+
+#define REG_A2XX_VGT_PERFCOUNTER3_HI				0x00000c53
+
+#define REG_A2XX_TCR_PERFCOUNTER0_SELECT			0x00000e05
+
+#define REG_A2XX_TCR_PERFCOUNTER1_SELECT			0x00000e08
+
+#define REG_A2XX_TCR_PERFCOUNTER0_HI				0x00000e06
+
+#define REG_A2XX_TCR_PERFCOUNTER1_HI				0x00000e09
+
+#define REG_A2XX_TCR_PERFCOUNTER0_LOW				0x00000e07
+
+#define REG_A2XX_TCR_PERFCOUNTER1_LOW				0x00000e0a
+
+#define REG_A2XX_TP0_PERFCOUNTER0_SELECT			0x00000e1f
+
+#define REG_A2XX_TP0_PERFCOUNTER0_HI				0x00000e20
+
+#define REG_A2XX_TP0_PERFCOUNTER0_LOW				0x00000e21
+
+#define REG_A2XX_TP0_PERFCOUNTER1_SELECT			0x00000e22
+
+#define REG_A2XX_TP0_PERFCOUNTER1_HI				0x00000e23
+
+#define REG_A2XX_TP0_PERFCOUNTER1_LOW				0x00000e24
+
+#define REG_A2XX_TCM_PERFCOUNTER0_SELECT			0x00000e54
+
+#define REG_A2XX_TCM_PERFCOUNTER1_SELECT			0x00000e57
+
+#define REG_A2XX_TCM_PERFCOUNTER0_HI				0x00000e55
+
+#define REG_A2XX_TCM_PERFCOUNTER1_HI				0x00000e58
+
+#define REG_A2XX_TCM_PERFCOUNTER0_LOW				0x00000e56
+
+#define REG_A2XX_TCM_PERFCOUNTER1_LOW				0x00000e59
+
+#define REG_A2XX_TCF_PERFCOUNTER0_SELECT			0x00000e5a
+
+#define REG_A2XX_TCF_PERFCOUNTER1_SELECT			0x00000e5d
+
+#define REG_A2XX_TCF_PERFCOUNTER2_SELECT			0x00000e60
+
+#define REG_A2XX_TCF_PERFCOUNTER3_SELECT			0x00000e63
+
+#define REG_A2XX_TCF_PERFCOUNTER4_SELECT			0x00000e66
+
+#define REG_A2XX_TCF_PERFCOUNTER5_SELECT			0x00000e69
+
+#define REG_A2XX_TCF_PERFCOUNTER6_SELECT			0x00000e6c
+
+#define REG_A2XX_TCF_PERFCOUNTER7_SELECT			0x00000e6f
+
+#define REG_A2XX_TCF_PERFCOUNTER8_SELECT			0x00000e72
+
+#define REG_A2XX_TCF_PERFCOUNTER9_SELECT			0x00000e75
+
+#define REG_A2XX_TCF_PERFCOUNTER10_SELECT			0x00000e78
+
+#define REG_A2XX_TCF_PERFCOUNTER11_SELECT			0x00000e7b
+
+#define REG_A2XX_TCF_PERFCOUNTER0_HI				0x00000e5b
+
+#define REG_A2XX_TCF_PERFCOUNTER1_HI				0x00000e5e
+
+#define REG_A2XX_TCF_PERFCOUNTER2_HI				0x00000e61
+
+#define REG_A2XX_TCF_PERFCOUNTER3_HI				0x00000e64
+
+#define REG_A2XX_TCF_PERFCOUNTER4_HI				0x00000e67
+
+#define REG_A2XX_TCF_PERFCOUNTER5_HI				0x00000e6a
+
+#define REG_A2XX_TCF_PERFCOUNTER6_HI				0x00000e6d
+
+#define REG_A2XX_TCF_PERFCOUNTER7_HI				0x00000e70
+
+#define REG_A2XX_TCF_PERFCOUNTER8_HI				0x00000e73
+
+#define REG_A2XX_TCF_PERFCOUNTER9_HI				0x00000e76
+
+#define REG_A2XX_TCF_PERFCOUNTER10_HI				0x00000e79
+
+#define REG_A2XX_TCF_PERFCOUNTER11_HI				0x00000e7c
+
+#define REG_A2XX_TCF_PERFCOUNTER0_LOW				0x00000e5c
+
+#define REG_A2XX_TCF_PERFCOUNTER1_LOW				0x00000e5f
+
+#define REG_A2XX_TCF_PERFCOUNTER2_LOW				0x00000e62
+
+#define REG_A2XX_TCF_PERFCOUNTER3_LOW				0x00000e65
+
+#define REG_A2XX_TCF_PERFCOUNTER4_LOW				0x00000e68
+
+#define REG_A2XX_TCF_PERFCOUNTER5_LOW				0x00000e6b
+
+#define REG_A2XX_TCF_PERFCOUNTER6_LOW				0x00000e6e
+
+#define REG_A2XX_TCF_PERFCOUNTER7_LOW				0x00000e71
+
+#define REG_A2XX_TCF_PERFCOUNTER8_LOW				0x00000e74
+
+#define REG_A2XX_TCF_PERFCOUNTER9_LOW				0x00000e77
+
+#define REG_A2XX_TCF_PERFCOUNTER10_LOW				0x00000e7a
+
+#define REG_A2XX_TCF_PERFCOUNTER11_LOW				0x00000e7d
+
+#define REG_A2XX_SQ_PERFCOUNTER0_SELECT				0x00000dc8
+
+#define REG_A2XX_SQ_PERFCOUNTER1_SELECT				0x00000dc9
+
+#define REG_A2XX_SQ_PERFCOUNTER2_SELECT				0x00000dca
+
+#define REG_A2XX_SQ_PERFCOUNTER3_SELECT				0x00000dcb
+
+#define REG_A2XX_SQ_PERFCOUNTER0_LOW				0x00000dcc
+
+#define REG_A2XX_SQ_PERFCOUNTER0_HI				0x00000dcd
+
+#define REG_A2XX_SQ_PERFCOUNTER1_LOW				0x00000dce
+
+#define REG_A2XX_SQ_PERFCOUNTER1_HI				0x00000dcf
+
+#define REG_A2XX_SQ_PERFCOUNTER2_LOW				0x00000dd0
+
+#define REG_A2XX_SQ_PERFCOUNTER2_HI				0x00000dd1
+
+#define REG_A2XX_SQ_PERFCOUNTER3_LOW				0x00000dd2
+
+#define REG_A2XX_SQ_PERFCOUNTER3_HI				0x00000dd3
+
+#define REG_A2XX_SX_PERFCOUNTER0_SELECT				0x00000dd4
+
+#define REG_A2XX_SX_PERFCOUNTER0_LOW				0x00000dd8
+
+#define REG_A2XX_SX_PERFCOUNTER0_HI				0x00000dd9
+
+#define REG_A2XX_MH_PERFCOUNTER0_SELECT				0x00000a46
+
+#define REG_A2XX_MH_PERFCOUNTER1_SELECT				0x00000a4a
+
+#define REG_A2XX_MH_PERFCOUNTER0_CONFIG				0x00000a47
+
+#define REG_A2XX_MH_PERFCOUNTER1_CONFIG				0x00000a4b
+
+#define REG_A2XX_MH_PERFCOUNTER0_LOW				0x00000a48
+
+#define REG_A2XX_MH_PERFCOUNTER1_LOW				0x00000a4c
+
+#define REG_A2XX_MH_PERFCOUNTER0_HI				0x00000a49
+
+#define REG_A2XX_MH_PERFCOUNTER1_HI				0x00000a4d
+
+#define REG_A2XX_RB_PERFCOUNTER0_SELECT				0x00000f04
+
+#define REG_A2XX_RB_PERFCOUNTER0_LOW				0x00000f08
+
+#define REG_A2XX_RB_PERFCOUNTER0_HI				0x00000f09
+
 #define REG_A2XX_SQ_TEX_0					0x00000000
 #define A2XX_SQ_TEX_0_TYPE__MASK				0x00000003
 #define A2XX_SQ_TEX_0_TYPE__SHIFT				0
@@ -1913,7 +2981,7 @@ static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val)
 {
 	return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK;
 }
-#define A2XX_SQ_TEX_0_TILED					0x00000002
+#define A2XX_SQ_TEX_0_TILED					0x80000000
 
 #define REG_A2XX_SQ_TEX_1					0x00000001
 #define A2XX_SQ_TEX_1_FORMAT__MASK				0x0000003f
@@ -2001,7 +3069,7 @@ static inline uint32_t A2XX_SQ_TEX_3_SWIZ_W(enum sq_tex_swiz val)
 }
 #define A2XX_SQ_TEX_3_EXP_ADJUST__MASK				0x0007e000
 #define A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT				13
-static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(uint32_t val)
+static inline uint32_t A2XX_SQ_TEX_3_EXP_ADJUST(int32_t val)
 {
 	return ((val) << A2XX_SQ_TEX_3_EXP_ADJUST__SHIFT) & A2XX_SQ_TEX_3_EXP_ADJUST__MASK;
 }