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| author | Vidya Srinivas <vidya.srinivas@intel.com> | 2018-05-12 03:03:13 +0530 |
|---|---|---|
| committer | Maarten Lankhorst <maarten.lankhorst@linux.intel.com> | 2018-05-11 10:19:43 +0200 |
| commit | 6deef9b6057d9432e08dab3643be92517e0d15de (patch) | |
| tree | c6df45aeb4604ccee41c551c03581e40176d7f3a /drivers/gpu/drm/i915/intel_sprite.c | |
| parent | 8e021151948c56eddf68affc6817965dabbcaddd (diff) | |
drm/i915: Enable Display WA 0528
Possible hang with NV12 plane surface formats.
WA: When the plane source pixel format is NV12,
the CHICKEN_PIPESL_* register bit 22 must be set to 1
and the render decompression must not be enabled
on any of the planes in that pipe.
v2: removed unnecessary POSTING_READ
v3: Added RB from Maarten
v4: Removed support for NV12 for BROXTON
Credits-to: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1526074397-10457-3-git-send-email-vidya.srinivas@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_sprite.c')
0 files changed, 0 insertions, 0 deletions