path: root/drivers/gpu/drm/i915/intel_lrc.c
diff options
authorDave Airlie <>2018-11-16 08:52:14 +1000
committerDave Airlie <>2018-11-16 08:52:14 +1000
commit20325e8a614377967644cf63050095c9f2ea8ab9 (patch)
tree978f172d1d3cf2cb3ed51f2a29ac16518be22a68 /drivers/gpu/drm/i915/intel_lrc.c
parent9826b1138e497dfb48f5cc64a82c219b4d0932da (diff)
parent6e8adf6f4a4fa57dd3bef6b70de96e2b7b311204 (diff)
Merge tag 'drm-intel-fixes-2018-11-15' of git:// into drm-fixesdrm-fixes-2018-11-16
- Fix Bugzilla #108712: Fix incorrect EU count report from kernel - Fix to account for scale factor when calculating initial phase on scaled output - Avoid too trigger-happy HPD storm detection and fix a race and an OOPS for MST systems. - Relocation race fix for Gen4/5 - A couple ICL fixes and dependencies for above Fixes:. Signed-off-by: Dave Airlie <> From: Joonas Lahtinen <> Link:
Diffstat (limited to 'drivers/gpu/drm/i915/intel_lrc.c')
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 43957bb37a42..37c94a54efcb 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -424,7 +424,8 @@ static u64 execlists_update_context(struct i915_request *rq)
reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail);
- /* True 32b PPGTT with dynamic page allocation: update PDP
+ /*
+ * True 32b PPGTT with dynamic page allocation: update PDP
* registers and point the unallocated PDPs to scratch page.
* PML4 is allocated during ppgtt init, so this is not needed
* in 48-bit mode.
@@ -432,6 +433,17 @@ static u64 execlists_update_context(struct i915_request *rq)
if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))
execlists_update_context_pdps(ppgtt, reg_state);
+ /*
+ * Make sure the context image is complete before we submit it to HW.
+ *
+ * Ostensibly, writes (including the WCB) should be flushed prior to
+ * an uncached write such as our mmio register access, the empirical
+ * evidence (esp. on Braswell) suggests that the WC write into memory
+ * may not be visible to the HW prior to the completion of the UC
+ * register write and that we may begin execution from the context
+ * before its image is complete leading to invalid PD chasing.
+ */
+ wmb();
return ce->lrc_desc;