diff options
| author | Gaurav K Singh <gaurav.k.singh@intel.com> | 2014-12-05 14:13:41 +0530 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-12-05 15:28:20 +0100 |
| commit | a9da9bce88ee842c7904b5670c035ca759e77238 (patch) | |
| tree | d5a078e15b1db6eaf2ae49570ae5acb7cd9b0e80 /drivers/gpu/drm/i915/intel_bios.h | |
| parent | 369602d370fac9d3bda125c8cc36c8f779910bf1 (diff) | |
drm/i915: Pixel Clock changes for DSI dual link
For dual link MIPI Panels, each port needs half of pixel clock. Pixel overlap
can be enabled if needed by panel, then in that case, pixel clock will be
increased for extra pixels.
v2 : Address review comments by Jani
- Removed the bit mask used for ->dual_link
- Used DSI instead of MIPI for #define variables
v3: Added the VLV_DISPLAY_BASE to VLV_CHICKEN_3 register
Signed-off-by: Gaurav K Singh <gaurav.k.singh@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_bios.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_bios.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_bios.h b/drivers/gpu/drm/i915/intel_bios.h index de01167d8a51..a6a8710f665f 100644 --- a/drivers/gpu/drm/i915/intel_bios.h +++ b/drivers/gpu/drm/i915/intel_bios.h @@ -818,7 +818,8 @@ struct mipi_config { #define DUAL_LINK_PIXEL_ALT 2 u16 dual_link:2; u16 lane_cnt:2; - u16 rsvd3:12; + u16 pixel_overlap:3; + u16 rsvd3:9; u16 rsvd4; |