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authorMatt Roper <matthew.d.roper@intel.com>2022-02-08 21:11:37 -0800
committerMatt Roper <matthew.d.roper@intel.com>2022-02-16 12:29:46 -0800
commitab9e00a3509ab7868cc3d4641f45ff926467b38c (patch)
treece48cf959860aaf8faed17625b1a6053e7746e3e /drivers/gpu/drm/i915/gt/intel_workarounds.c
parent93cc7aa0b037f34d9a55c58fb4ab6bbd802fa47c (diff)
drm/i915/gt: Use parameterized RING_MI_MODE
We have both a parameterized RING_MI_MODE() macro and an RCS-specific MI_MODE; drop the latter and use the former everywhere. Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220209051140.1599643-4-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_workarounds.c')
-rw-r--r--drivers/gpu/drm/i915/gt/intel_workarounds.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 59ad23118875..eeda1692d845 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -237,7 +237,7 @@ static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_masked_en(wal, INSTPM, INSTPM_FORCE_ORDERING);
/* WaDisableAsyncFlipPerfMode:bdw,chv */
- wa_masked_en(wal, MI_MODE, ASYNC_FLIP_PERF_DISABLE);
+ wa_masked_en(wal, RING_MI_MODE(RENDER_RING_BASE), ASYNC_FLIP_PERF_DISABLE);
/* WaDisablePartialInstShootdown:bdw,chv */
wa_masked_en(wal, GEN8_ROW_CHICKEN,
@@ -2463,7 +2463,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
*/
wa_masked_en(wal,
- MI_MODE,
+ RING_MI_MODE(RENDER_RING_BASE),
ASYNC_FLIP_PERF_DISABLE);
if (GRAPHICS_VER(i915) == 6) {
@@ -2522,7 +2522,7 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
if (IS_GRAPHICS_VER(i915, 4, 6))
/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
- wa_add(wal, MI_MODE,
+ wa_add(wal, RING_MI_MODE(RENDER_RING_BASE),
0, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH),
/* XXX bit doesn't stick on Broadwater */
IS_I965G(i915) ? 0 : VS_TIMER_DISPATCH, true);