diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-03-03 21:12:07 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-03-21 18:00:15 +0200 |
| commit | ea0839691816b9742ca1371d4e1645192f1a733d (patch) | |
| tree | ddb95944a4f71f18ac9df0526ce00e16bbe4051d /drivers/gpu/drm/i915/display/intel_bw.h | |
| parent | 5ac860cc52540df8bca27e0bb25b6744df67e8f0 (diff) | |
drm/i915: Add "maximum pipe read bandwidth" checks
Make sure the CDCLK is high enough to support the so called
"maximum pipe read bandwidth" limitation. Specified as
51.2 x CDCLK.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220303191207.27931-10-ville.syrjala@linux.intel.com
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_bw.h')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_bw.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index 92fc09a8c824..cb7ee3a24a58 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.h +++ b/drivers/gpu/drm/i915/display/intel_bw.h @@ -41,6 +41,7 @@ struct intel_bw_state { */ u16 qgv_points_mask; + int min_cdclk[I915_MAX_PIPES]; unsigned int data_rate[I915_MAX_PIPES]; u8 num_active_planes[I915_MAX_PIPES]; }; |