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authorVille Syrjälä <ville.syrjala@linux.intel.com>2019-06-04 23:09:29 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2019-06-12 14:41:21 +0300
commitb16c7ed95caf270075c52faad0af8f4cb57ae979 (patch)
tree89f0ea79f0f2383be21a35b6a24942c54069b135 /drivers/gpu/drm/amd
parent33df8a7697a08ec96811a1e9bbce45c7cdbbc316 (diff)
drm/i915: Do not touch the PCH SSC reference if a PLL is using it
Our PCH refclk init code currently assumes that the PCH SSC reference can only be used for FDI. That is not true and it can be used by SPLL/WRPLL for eDP SSC or clock bending as well. Before we go reconfiguring it let's make sure no PLL is currently using the PCH SSC reference. For some reason the hw is not particularly upset about losing the clock if we immediately follow up with a modeset. Can't really explain why nothing times out during the crtc disable at least, but that's what the logs say. With fastboot the story is quite different and we lose the entire display if we turn off the PCH SSC reference when it's still being used. Since we totally skip configuring the PCH SSC reference it may not be in the proper state for FDI. Hopefully that won't be a problem in practice. We really should move this code to be part of the modeset seqeuence and properly deal with the potentially conflicting requirements imposed on PLL reference clocks. But that requires actual work. Let's toss in a TODO for that. v2: Pimp the commit message with the fastboot vs. not details Cc: Julius B. <freedesktop@blln.gr> Cc: Johannes Krampf <johannes.krampf@gmail.com> Tested-by: Johannes Krampf <johannes.krampf@gmail.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108773 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190604200933.29417-1-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/amd')
0 files changed, 0 insertions, 0 deletions