diff options
| author | Prike Liang <Prike.Liang@amd.com> | 2020-03-02 09:36:15 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-03-05 00:32:05 -0500 |
| commit | ffbed184d209bb44504fd2cd460db70176765818 (patch) | |
| tree | f25abead31eb965f1f8f19f4d80511e63e65d38f /drivers/gpu/drm/amd/powerplay/smu_v12_0.c | |
| parent | 8a43cf88b7d66e44140a5a48a2ff861c9c416ab0 (diff) | |
drm/amd/powerplay: fix pre-check condition for setting clock range
This fix will handle some MP1 FW issue like as mclk dpm table in renoir has a reverse
dpm clock layout and a zero frequency dpm level as following case.
cat pp_dpm_mclk
0: 1200Mhz
1: 1200Mhz
2: 800Mhz
3: 0Mhz
Signed-off-by: Prike Liang <Prike.Liang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/smu_v12_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/powerplay/smu_v12_0.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c index 93b85585fd26..d52e624f16d3 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v12_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v12_0.c @@ -461,9 +461,6 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_ { int ret = 0; - if (max < min) - return -EINVAL; - switch (clk_type) { case SMU_GFXCLK: case SMU_SCLK: |