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authorEvan Quan <evan.quan@amd.com>2020-07-08 12:45:00 +0800
committerAlex Deucher <alexander.deucher@amd.com>2020-07-21 15:37:38 -0400
commitd8e0b16d818ebd76386029fe098cddbae49bfaf5 (patch)
tree184b5f5203359afbbffeac4ff0c309ffa0015493 /drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
parent704759315a7c906147c9aa5f2a9a7b6145226a98 (diff)
drm/amd/powerplay: tag swSMU code layers
Per designs, the swSMU code is separated into four layers. And the typical calling flow should be like: amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c -> smu_cmn.c. Compile errors will come out for any violations. This can help to prevent cross callings(e.g. amdgpu_smu.c -> ${asic}_ppt.c -> amdgpu_smu.c -> ${asic}_ppt.c) which were common in our code. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h')
-rw-r--r--drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
index 52cdd6a0f99a..02de3b6199e5 100644
--- a/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
+++ b/drivers/gpu/drm/amd/powerplay/inc/smu_v12_0.h
@@ -31,6 +31,8 @@
#define MP1_Public 0x03b00000
#define MP1_SRAM 0x03c00004
+#if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
+
int smu_v12_0_check_fw_status(struct smu_context *smu);
int smu_v12_0_check_fw_version(struct smu_context *smu);
@@ -59,3 +61,4 @@ int smu_v12_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_
int smu_v12_0_set_driver_table_location(struct smu_context *smu);
#endif
+#endif