diff options
| author | Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> | 2019-07-25 15:51:09 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-29 15:52:32 -0500 |
| commit | ff54ecb095b549a8e79ee87922cecdba69f6bb79 (patch) | |
| tree | 78f651470cc6ba6a2e0665ff3b4fa42b17fc8ae2 /drivers/gpu/drm/amd/display/dc | |
| parent | b593bce59bfa25d9abbf220b6614396ccd965b1b (diff) | |
drm/amd/display: Add Renoir clock registers list
These are the registers used to program the clock hw.
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h index adae03b1f3a7..43c1bf60b83c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h @@ -78,6 +78,23 @@ SRII(PIXEL_RATE_CNTL, OTG, 5) #endif +#if defined(CONFIG_DRM_AMD_DC_DCN2_1) +#define CS_COMMON_REG_LIST_DCN2_1(index, pllid) \ + SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ + SRII(PHASE, DP_DTO, 0),\ + SRII(PHASE, DP_DTO, 1),\ + SRII(PHASE, DP_DTO, 2),\ + SRII(PHASE, DP_DTO, 3),\ + SRII(MODULO, DP_DTO, 0),\ + SRII(MODULO, DP_DTO, 1),\ + SRII(MODULO, DP_DTO, 2),\ + SRII(MODULO, DP_DTO, 3),\ + SRII(PIXEL_RATE_CNTL, OTG, 0),\ + SRII(PIXEL_RATE_CNTL, OTG, 1),\ + SRII(PIXEL_RATE_CNTL, OTG, 2),\ + SRII(PIXEL_RATE_CNTL, OTG, 3) +#endif + #if defined(CONFIG_DRM_AMD_DC_DCN2_0) #define CS_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ |