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authorBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>2019-07-26 17:16:47 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-08-29 15:52:33 -0500
commitaa91916770d07cafafd24905b20e5350eb2dee30 (patch)
treeea0e79c5ea5fd6301d148aee9d54b25cd7047974 /drivers/gpu/drm/amd/display/dc
parentdd44a63386e052304e965a36902bb3ce69ff665a (diff)
drm/amd/display: add dcn21 core DC changes
Add missing parameters, to make dcn21 compile without errors Acked-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc')
-rw-r--r--drivers/gpu/drm/amd/display/dc/dc.h3
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/core_types.h3
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h4
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h1
4 files changed, 11 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 42b6a6e41c0b..a82352a87808 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -386,6 +386,9 @@ struct dc_debug_options {
#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
bool disable_fec;
#endif
+#ifdef CONFIG_DRM_AMD_DC_DCN2_1
+ bool disable_48mhz_pwrdwn;
+#endif
/* This forces a hard min on the DCFCLK requested to SMU/PP
* watermarks are not affected.
*/
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index 8726bd7dd910..f189307750ab 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -87,6 +87,9 @@ void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable);
struct resource_pool;
struct dc_state;
struct resource_context;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+struct clk_bw_params;
+#endif
struct resource_funcs {
void (*destroy)(struct resource_pool **pool);
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
index 7193acfcd779..e8668388581b 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h
@@ -40,6 +40,10 @@ struct cstate_pstate_watermarks_st {
struct dcn_watermarks {
uint32_t pte_meta_urgent_ns;
uint32_t urgent_ns;
+#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
+ uint32_t frac_urg_bw_nom;
+ uint32_t frac_urg_bw_flip;
+#endif
struct cstate_pstate_watermarks_st cstate_pstate;
};
diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index 732a93df1844..3a938cd414ea 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -48,6 +48,7 @@ struct dce_hwseq_wa {
bool DEGVIDCN10_253;
bool false_optc_underflow;
bool DEGVIDCN10_254;
+ bool DEGVIDCN21;
};
struct hwseq_wa_state {