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authorBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>2020-05-21 12:45:45 -0400
committerAlex Deucher <alexander.deucher@amd.com>2020-07-01 01:59:15 -0400
commitd99f13878d6f9c286b13860d8bf0b4db9ffb189a (patch)
treea64a028d9c3cfc5c480b8125f876e7206e24e5b1 /drivers/gpu/drm/amd/display/dc/inc/core_types.h
parent5baebf61ba0ce14253a513ac92be661b35a19676 (diff)
drm/amd/display: Add DCN3 HWSEQ
Add HW sequence programing for DCN3 Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/core_types.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/core_types.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
index c7fd702a4a87..654dcdb4aba6 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h
@@ -217,6 +217,10 @@ struct resource_pool {
struct dmcu *dmcu;
struct dmub_psr *psr;
+#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
+ struct abm *multiple_abms[MAX_PIPES];
+#endif
+
const struct resource_funcs *funcs;
const struct resource_caps *res_cap;