diff options
| author | Yu-ting Shen <Yu-ting.Shen@amd.com> | 2020-02-07 15:19:31 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2020-02-25 11:10:08 -0500 |
| commit | cab5dec425f19f3d4eeca0d8e073578cbed66d8d (patch) | |
| tree | fde65b894009996b7a244bd03c449e43967b0b8b /drivers/gpu/drm/amd/display/dc/dcn21 | |
| parent | e2c9529f00419dd4d4c8b62defeb3300eee683f2 (diff) | |
drm/amd/display: limit display clock to 100MHz to avoid FIFO error
[Why]
when changing display clock, SMU need to use power up DFS and use
DENTIST to ramp DFS DID to switch target frequency before switching back
to bypass.
[How]
fixed the minimum display clock to 100MHz, it's W/A the same with PCO.
Signed-off-by: Yu-ting Shen <Yu-ting.Shen@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dcn21')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c index aa73025c1747..dce4966eca20 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c @@ -859,6 +859,7 @@ static const struct dc_debug_options debug_defaults_drv = { .timing_trace = false, .clock_trace = true, .disable_pplib_clock_request = true, + .min_disp_clk_khz = 100000, .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP, .force_single_disp_pipe_split = false, .disable_dcc = DCC_ENABLE, |