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authorNikola Cornij <nikola.cornij@amd.com>2019-06-25 17:19:25 -0400
committerAlex Deucher <alexander.deucher@amd.com>2019-07-18 14:27:25 -0500
commitd68a74541735e030dea56f72746cd26d19986f41 (patch)
tree86e5338ef2a5c3c0d279793c73d16980794c81fa /drivers/gpu/drm/amd/display/dc/core
parente752058b8671c6c87e484cff144c5c6309a37253 (diff)
drm/amd/display: Clear FEC_READY shadow register if DPCD write fails
[why] As a fail-safe, in case 'set FEC_READY' DPCD write fails, a HW shadow register should be cleared and the internal FEC stat should be set to 'not ready'. This is to make sure HW settings will be consistent with FEC_READY state on the RX. Signed-off-by: Nikola Cornij <nikola.cornij@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Chris Park <Chris.Park@amd.com> Acked-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/core')
-rw-r--r--drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 5c8e3318239c..b512fecae061 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -3174,6 +3174,8 @@ void dp_set_fec_ready(struct dc_link *link, bool ready)
link_enc->funcs->fec_set_ready(link_enc, true);
link->fec_state = dc_link_fec_ready;
} else {
+ link->link_enc->funcs->fec_set_ready(link->link_enc, false);
+ link->fec_state = dc_link_fec_not_ready;
dm_error("dpcd write failed to set fec_ready");
}
} else if (link->fec_state == dc_link_fec_ready) {