diff options
| author | Joshua Aberback <joshua.aberback@amd.com> | 2019-04-01 15:18:29 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-06-22 09:34:09 -0500 |
| commit | 254eb07cb090374d0e1e90790395ead77f6f6ad5 (patch) | |
| tree | e8e3e08e14a735329d80aa93460f216867678711 /drivers/gpu/drm/amd/display/dc/calcs | |
| parent | 776c1f569f94e39a1776c22f29137661f294ff03 (diff) | |
drm/amd/display: Optimize bandwidth validation by adding early return
We can split validation into three parts: getting voltage level, getting
watermarks, and rq/dlg calculations. The voltage level is enough to answer
the question "do we support this state", and the rest of it is to determine
what hardware programming is needed to support the state. Most of the calls
to validate_bandwidth only care about the first part, so we added an early
return in that case
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/calcs')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index ef804948694e..38365dd911a3 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -1116,9 +1116,8 @@ bool dcn_validate_bandwidth( context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / (ddr4_dram_factor_single_Channel * v->number_of_channels)); - if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) { + if (bw_consumed == v->fabric_and_dram_bandwidth_vmin0p65) context->bw_ctx.bw.dcn.clk.fclk_khz = (int)(bw_consumed * 1000000 / 32); - } context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000); context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(v->dcfclk * 1000); @@ -1133,7 +1132,8 @@ bool dcn_validate_bandwidth( dc->debug.min_disp_clk_khz; } - context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / v->dispclk_dppclk_ratio; + context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / + v->dispclk_dppclk_ratio; context->bw_ctx.bw.dcn.clk.phyclk_khz = v->phyclk_per_state[v->voltage_level]; switch (v->voltage_level) { case 0: @@ -1220,9 +1220,7 @@ bool dcn_validate_bandwidth( /* pipe not split previously needs split */ hsplit_pipe = find_idle_secondary_pipe(&context->res_ctx, pool, pipe); ASSERT(hsplit_pipe); - split_stream_across_pipes( - &context->res_ctx, pool, - pipe, hsplit_pipe); + split_stream_across_pipes(&context->res_ctx, pool, pipe, hsplit_pipe); } dcn_bw_calc_rq_dlg_ttu(dc, v, hsplit_pipe, input_idx); @@ -1253,7 +1251,6 @@ bool dcn_validate_bandwidth( } if (v->voltage_level == 0) { - context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->dcn_soc->sr_enter_plus_exit_time; context->bw_ctx.dml.soc.sr_exit_time_us = dc->dcn_soc->sr_exit_time; |