diff options
| author | Alexandre Ghiti <alexghiti@rivosinc.com> | 2023-12-12 22:34:56 +0100 |
|---|---|---|
| committer | Dennis Zhou <dennis@kernel.org> | 2023-12-14 00:23:17 -0800 |
| commit | 7a92fc8b4d20680e4c20289a670d8fca2d1f2c1b (patch) | |
| tree | f02aada180e46f0f74910d88d85b96c0f181061e /arch/arc | |
| parent | 33cc938e65a98f1d29d0a18403dbbee050dcad9a (diff) | |
mm: Introduce flush_cache_vmap_early()
The pcpu setup when using the page allocator sets up a new vmalloc
mapping very early in the boot process, so early that it cannot use the
flush_cache_vmap() function which may depend on structures not yet
initialized (for example in riscv, we currently send an IPI to flush
other cpus TLB).
But on some architectures, we must call flush_cache_vmap(): for example,
in riscv, some uarchs can cache invalid TLB entries so we need to flush
the new established mapping to avoid taking an exception.
So fix this by introducing a new function flush_cache_vmap_early() which
is called right after setting the new page table entry and before
accessing this new mapping. This new function implements a local flush
tlb on riscv and is no-op for other architectures (same as today).
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Dennis Zhou <dennis@kernel.org>
Diffstat (limited to 'arch/arc')
| -rw-r--r-- | arch/arc/include/asm/cacheflush.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arc/include/asm/cacheflush.h b/arch/arc/include/asm/cacheflush.h index bd5b1a9a0544..6fc74500a9f5 100644 --- a/arch/arc/include/asm/cacheflush.h +++ b/arch/arc/include/asm/cacheflush.h @@ -40,6 +40,7 @@ void dma_cache_wback(phys_addr_t start, unsigned long sz); /* TBD: optimize this */ #define flush_cache_vmap(start, end) flush_cache_all() +#define flush_cache_vmap_early(start, end) do { } while (0) #define flush_cache_vunmap(start, end) flush_cache_all() #define flush_cache_dup_mm(mm) /* called on fork (VIVT only) */ |