From e07f541f50a31541f761300aa8bf6e3008ac448b Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Tue, 19 Dec 2017 16:47:02 -0500 Subject: drm/amd/display: Use real BE and FE index to program regs. In case of some pipes are fused, pipe_idx should not be used to program pipe regs. Instead of that, BE and FE inst number should be used for reg index. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/dc/inc/core_types.h') diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index d6971054ec07..8dcaf91dd071 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -188,6 +188,7 @@ struct plane_resource { struct input_pixel_processor *ipp; struct transform *xfm; struct dpp *dpp; + uint8_t mpcc_inst; }; struct pipe_ctx { -- cgit v1.2.3 From e56ae556e16265de6cc237d14a9a1518dbbcb807 Mon Sep 17 00:00:00 2001 From: Nikola Cornij Date: Thu, 14 Dec 2017 17:57:56 -0500 Subject: drm/amd/display: Define remove_stream_from_ctx resource func This will allow us to clean up resources on a stream as needed. Signed-off-by: Nikola Cornij Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 3 +++ drivers/gpu/drm/amd/display/dc/inc/core_types.h | 5 +++++ 2 files changed, 8 insertions(+) (limited to 'drivers/gpu/drm/amd/display/dc/inc/core_types.h') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 36d54ef5cae2..ba88284d305a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1554,6 +1554,9 @@ enum dc_status dc_remove_stream_from_ctx( dc->res_pool, del_pipe->clock_source); + if (dc->res_pool->funcs->remove_stream_from_ctx) + dc->res_pool->funcs->remove_stream_from_ctx(dc, new_ctx, stream); + memset(del_pipe, 0, sizeof(*del_pipe)); break; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 8dcaf91dd071..59d2699b17ce 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -119,6 +119,11 @@ struct resource_funcs { struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream); + + enum dc_status (*remove_stream_from_ctx)( + struct dc *dc, + struct dc_state *new_ctx, + struct dc_stream_state *stream); }; struct audio_support{ -- cgit v1.2.3 From 3be1406a72b08e3122660f7ea2a41a129fe5e266 Mon Sep 17 00:00:00 2001 From: Yongqiang Sun Date: Fri, 5 Jan 2018 13:53:06 -0500 Subject: drm/amd/display: Add timing generator count to resource pool. Use tg count in resource pool for further reference. Signed-off-by: Yongqiang Sun Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c | 2 +- drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c | 1 + drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c | 3 +++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 6 +++--- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + drivers/gpu/drm/amd/display/dc/inc/core_types.h | 1 + 8 files changed, 12 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/core_types.h') diff --git a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c index 442dd2d93618..3bdbed80f7f8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c @@ -849,6 +849,7 @@ static bool construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap.num_timing_generator; + pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; dc->caps.max_cursor_size = 128; diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c index 0f84306dd28e..c4e877ac95d3 100644 --- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c @@ -1152,7 +1152,7 @@ static bool construct( pool->base.pipe_count = pool->base.res_cap->num_timing_generator; pool->base.underlay_pipe_index = pool->base.pipe_count; - + pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; dc->caps.max_downscale_ratio = 150; dc->caps.i2c_speed_in_khz = 100; dc->caps.max_cursor_size = 128; diff --git a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c index 98d9cd0109e1..c0757dd6c03c 100644 --- a/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c @@ -1100,6 +1100,7 @@ static bool construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = pool->base.res_cap->num_timing_generator; + pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 100; dc->caps.max_cursor_size = 128; diff --git a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c index a8725ac11a2c..4659a4bfabaa 100644 --- a/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c @@ -831,6 +831,7 @@ static bool construct( /* TODO: Fill more data from GreenlandAsicCapability.cpp */ pool->base.pipe_count = res_cap.num_timing_generator; + pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; dc->caps.max_downscale_ratio = 200; diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c index 25d7eb1567ae..a36c14d3d9a8 100644 --- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c @@ -790,6 +790,7 @@ static bool dce80_construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap.num_timing_generator; + pool->base.timing_generator_count = res_cap.num_timing_generator; dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; dc->caps.max_cursor_size = 128; @@ -955,6 +956,7 @@ static bool dce81_construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap_81.num_timing_generator; + pool->base.timing_generator_count = res_cap_81.num_timing_generator; dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; dc->caps.max_cursor_size = 128; @@ -1120,6 +1122,7 @@ static bool dce83_construct( *************************************************/ pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; pool->base.pipe_count = res_cap_83.num_timing_generator; + pool->base.timing_generator_count = res_cap_83.num_timing_generator; dc->caps.max_downscale_ratio = 200; dc->caps.i2c_speed_in_khz = 40; dc->caps.max_cursor_size = 128; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index c6a4fa2f17c2..e1a8ebae3714 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -133,7 +133,7 @@ void dcn10_log_hw_state(struct dc *dc) DTN_INFO("[%d]:\t %xh \t %xh \t %d \t %d \t " "%xh \t %xh \t %xh \t " "%d \t %d \t %d \t %xh \t", - i, + hubp->inst, s.pixel_format, s.inuse_addr_hi, s.viewport_width, @@ -155,7 +155,7 @@ void dcn10_log_hw_state(struct dc *dc) DTN_INFO("OTG:\t v_bs \t v_be \t v_ss \t v_se \t vpol \t vmax \t vmin \t " "h_bs \t h_be \t h_ss \t h_se \t hpol \t htot \t vtot \t underflow\n"); - for (i = 0; i < pool->res_cap->num_timing_generator; i++) { + for (i = 0; i < pool->timing_generator_count; i++) { struct timing_generator *tg = pool->timing_generators[i]; struct dcn_otg_state s = {0}; @@ -168,7 +168,7 @@ void dcn10_log_hw_state(struct dc *dc) DTN_INFO("[%d]:\t %d \t %d \t %d \t %d \t " "%d \t %d \t %d \t %d \t %d \t %d \t " "%d \t %d \t %d \t %d \t %d \t ", - i, + tg->inst, s.v_blank_start, s.v_blank_end, s.v_sync_a_start, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 66af05b03e0f..ed616f5e4265 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -1445,6 +1445,7 @@ static bool construct( /* valid pipe num */ pool->base.pipe_count = j; + pool->base.timing_generator_count = j; /* within dml lib, it is hard code to 4. If ASIC pipe is fused, * the value may be changed diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 59d2699b17ce..5509e13e7edf 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -153,6 +153,7 @@ struct resource_pool { unsigned int underlay_pipe_index; unsigned int stream_enc_count; unsigned int ref_clock_inKhz; + unsigned int timing_generator_count; /* * reserved clock source for DP -- cgit v1.2.3 From f553e6810259d8bd31a4b9ac3001cfcde7f8fb7e Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Mon, 12 Feb 2018 15:19:20 -0500 Subject: drm/amd/display: add per pipe dppclk v2: Fix commit title Signed-off-by: Dmytro Laktyushkin Reviewed-by: Tony Cheng Acked-by: Harry Wentland Acked-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc_debug.c | 13 +++++++------ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c | 6 ++---- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 9 +++++---- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 15 +++++++++++++-- 5 files changed, 28 insertions(+), 17 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/core_types.h') diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c index c9aa686d16b9..e4d8a8dbc5ef 100644 --- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c @@ -996,7 +996,7 @@ bool dcn_validate_bandwidth( dc->debug.min_disp_clk_khz; } - context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2; + context->bw.dcn.calc_clk.max_dppclk_khz = (int)(v->dppclk * 1000); for (i = 0, input_idx = 0; i < pool->pipe_count; i++) { struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i]; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c index 1babac07bcc9..c15565092ca8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_debug.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_debug.c @@ -361,21 +361,22 @@ void context_clock_trace( struct dc *core_dc = dc; struct dal_logger *logger = core_dc->ctx->logger; - CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n" - "dcfclk_deep_sleep_khz:%d fclk_khz:%d\n" + CLOCK_TRACE("Current: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n" + "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n" "dram_ccm_us:%d min_active_dram_ccm_us:%d\n", context->bw.dcn.calc_clk.dispclk_khz, - context->bw.dcn.calc_clk.dppclk_div, + context->bw.dcn.calc_clk.max_dppclk_khz, context->bw.dcn.calc_clk.dcfclk_khz, context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz, context->bw.dcn.calc_clk.fclk_khz, + context->bw.dcn.calc_clk.socclk_khz, context->bw.dcn.calc_clk.dram_ccm_us, context->bw.dcn.calc_clk.min_active_dram_ccm_us); - CLOCK_TRACE("Calculated: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n" - "dcfclk_deep_sleep_khz:%d fclk_khz:%d\n" + CLOCK_TRACE("Calculated: dispclk_khz:%d max_dppclk_khz:%d dcfclk_khz:%d\n" + "dcfclk_deep_sleep_khz:%d fclk_khz:%d socclk_khz:%d\n" "dram_ccm_us:%d min_active_dram_ccm_us:%d\n", context->bw.dcn.calc_clk.dispclk_khz, - context->bw.dcn.calc_clk.dppclk_div, + context->bw.dcn.calc_clk.max_dppclk_khz, context->bw.dcn.calc_clk.dcfclk_khz, context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz, context->bw.dcn.calc_clk.fclk_khz, diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c index 8725cab9ec00..f0b798930b51 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c @@ -432,14 +432,12 @@ void dpp1_dppclk_control( struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); if (enable) { - if (dpp->tf_mask->DPPCLK_RATE_CONTROL) { + if (dpp->tf_mask->DPPCLK_RATE_CONTROL) REG_UPDATE_2(DPP_CONTROL, DPPCLK_RATE_CONTROL, dppclk_div, DPP_CLOCK_ENABLE, 1); - } else { - ASSERT(dppclk_div == false); + else REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1); - } } else REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0); } diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 7a1b2deaf3d7..759e925439ce 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1684,12 +1684,13 @@ static void update_dchubp_dpp( if (plane_state->update_flags.bits.full_update) { dpp->funcs->dpp_dppclk_control( dpp, - context->bw.dcn.calc_clk.dppclk_div, + context->bw.dcn.calc_clk.max_dppclk_khz < + context->bw.dcn.calc_clk.dispclk_khz, true); - dc->current_state->bw.dcn.cur_clk.dppclk_div = - context->bw.dcn.calc_clk.dppclk_div; - context->bw.dcn.cur_clk.dppclk_div = context->bw.dcn.calc_clk.dppclk_div; + dc->current_state->bw.dcn.cur_clk.max_dppclk_khz = + context->bw.dcn.calc_clk.max_dppclk_khz; + context->bw.dcn.cur_clk.max_dppclk_khz = context->bw.dcn.calc_clk.max_dppclk_khz; } /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 5509e13e7edf..a9b21a4a0c17 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -177,6 +177,15 @@ struct resource_pool { const struct resource_caps *res_cap; }; +struct dcn_fe_clocks { + int dppclk_khz; +}; + +struct dcn_fe_bandwidth { + struct dcn_fe_clocks calc; + struct dcn_fe_clocks cur; +}; + struct stream_resource { struct output_pixel_processor *opp; struct timing_generator *tg; @@ -195,6 +204,8 @@ struct plane_resource { struct transform *xfm; struct dpp *dpp; uint8_t mpcc_inst; + + struct dcn_fe_bandwidth bw; }; struct pipe_ctx { @@ -247,9 +258,9 @@ struct dce_bw_output { struct dcn_bw_clocks { int dispclk_khz; - int dppclk_khz; - bool dppclk_div; + int max_dppclk_khz; int dcfclk_khz; + int socclk_khz; int dcfclk_deep_sleep_khz; int fclk_khz; int dram_ccm_us; -- cgit v1.2.3 From 15cf3974eb06e7b6be1f8f02581759b5f3d9f1e4 Mon Sep 17 00:00:00 2001 From: Dmytro Laktyushkin Date: Tue, 13 Feb 2018 14:41:51 -0500 Subject: drm/amd/display: add diags clock programming Signed-off-by: Dmytro Laktyushkin Reviewed-by: Dmytro Laktyushkin Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 +++++ drivers/gpu/drm/amd/display/dc/dc.h | 11 +++++++++++ drivers/gpu/drm/amd/display/dc/dm_helpers.h | 3 +++ drivers/gpu/drm/amd/display/dc/inc/core_types.h | 15 ++------------- 4 files changed, 21 insertions(+), 13 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/core_types.h') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 3e157e65d7cd..9ab69b22b989 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -505,3 +505,8 @@ enum dc_edid_status dm_helpers_read_local_edid( return edid_status; } + +void dm_set_dcn_clocks(struct dc_context *ctx, struct dc_clocks *clks) +{ + /* TODO: something */ +} diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index a6402c651251..14cc4beb12c1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -184,6 +184,17 @@ enum wm_report_mode { WM_REPORT_OVERRIDE = 1, }; +struct dc_clocks { + int dispclk_khz; + int max_dppclk_khz; + int dcfclk_khz; + int socclk_khz; + int dcfclk_deep_sleep_khz; + int fclk_khz; + int dram_ccm_us; + int min_active_dram_ccm_us; +}; + struct dc_debug { bool surface_visual_confirm; bool sanity_checks; diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h index 53d5566f89b8..034369fbb9e2 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -108,5 +108,8 @@ enum dc_edid_status dm_helpers_read_local_edid( struct dc_link *link, struct dc_sink *sink); +void dm_set_dcn_clocks( + struct dc_context *ctx, + struct dc_clocks *clks); #endif /* __DM_HELPERS__ */ diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index a9b21a4a0c17..b8f05384a897 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -256,20 +256,9 @@ struct dce_bw_output { int blackout_recovery_time_us; }; -struct dcn_bw_clocks { - int dispclk_khz; - int max_dppclk_khz; - int dcfclk_khz; - int socclk_khz; - int dcfclk_deep_sleep_khz; - int fclk_khz; - int dram_ccm_us; - int min_active_dram_ccm_us; -}; - struct dcn_bw_output { - struct dcn_bw_clocks cur_clk; - struct dcn_bw_clocks calc_clk; + struct dc_clocks cur_clk; + struct dc_clocks calc_clk; struct dcn_watermark_set watermarks; }; -- cgit v1.2.3 From 9aef1a31709076660f7d5f638ab5ecadea4ca856 Mon Sep 17 00:00:00 2001 From: SivapiriyanKumarasamy Date: Fri, 23 Feb 2018 13:04:13 -0500 Subject: drm/amd/display: Varibright fix bug and review comments Fix bug and make changes from review 132656 Signed-off-by: SivapiriyanKumarasamy Reviewed-by: Tony Cheng Acked-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 14 +++++++----- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 +++++ drivers/gpu/drm/amd/display/dc/dc.h | 5 ----- drivers/gpu/drm/amd/display/dc/dc_stream.h | 4 ++-- .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 25 ++++++++++++++++------ .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 1 + drivers/gpu/drm/amd/display/dc/inc/core_types.h | 2 ++ 7 files changed, 37 insertions(+), 19 deletions(-) (limited to 'drivers/gpu/drm/amd/display/dc/inc/core_types.h') diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a0b91eeb1939..40a65cb9ee23 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1363,11 +1363,15 @@ static void commit_planes_for_stream(struct dc *dc, dc->hwss.apply_ctx_for_surface( dc, pipe_ctx->stream, stream_status->plane_count, context); - if (stream_update->abm_setting.stream_update) { - if (dc->res_pool->abm) - dc->res_pool->abm->funcs->set_abm_level( - dc->res_pool->abm, stream->abm_settings.abm_level); - stream->abm_settings.stream_update = 0; + if (stream_update->abm_level && pipe_ctx->stream_res.abm) { + if (pipe_ctx->stream_res.tg->funcs->is_blanked) { + // if otg funcs defined check if blanked before programming + if (!pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) + pipe_ctx->stream_res.abm->funcs->set_abm_level( + pipe_ctx->stream_res.abm, stream->abm_level); + } else + pipe_ctx->stream_res.abm->funcs->set_abm_level( + pipe_ctx->stream_res.abm, stream->abm_level); } } } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index b9fc6d842931..ba3487e97361 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1124,6 +1124,7 @@ bool dc_add_plane_to_context( ASSERT(tail_pipe); free_pipe->stream_res.tg = tail_pipe->stream_res.tg; + free_pipe->stream_res.abm = tail_pipe->stream_res.abm; free_pipe->stream_res.opp = tail_pipe->stream_res.opp; free_pipe->stream_res.stream_enc = tail_pipe->stream_res.stream_enc; free_pipe->stream_res.audio = tail_pipe->stream_res.audio; @@ -1736,6 +1737,10 @@ enum dc_status resource_map_pool_resources( pipe_ctx->stream_res.audio, true); } + /* Add ABM to the resource if on EDP */ + if (pipe_ctx->stream && dc_is_embedded_signal(pipe_ctx->stream->signal)) + pipe_ctx->stream_res.abm = pool->abm; + for (i = 0; i < context->stream_count; i++) if (context->streams[i] == stream) { context->stream_status[i].primary_otg_inst = pipe_ctx->stream_res.tg->inst; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index bf4f2e6960cb..2cd97342bf0f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -60,11 +60,6 @@ struct dc_versions { struct dmcu_version dmcu_version; }; -struct abm_setting { - bool stream_update; - unsigned int abm_level; -}; - struct dc_caps { uint32_t max_streams; uint32_t max_links; diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 76189418cbfa..bafe3889676f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -75,7 +75,7 @@ struct dc_stream_state { /* TODO: CEA VIC */ /* DMCU info */ - struct abm_setting abm_settings; + unsigned int abm_level; /* from core_stream struct */ struct dc_context *ctx; @@ -109,7 +109,7 @@ struct dc_stream_update { struct dc_transfer_func *out_transfer_func; struct dc_hdr_static_metadata *hdr_static_metadata; enum color_transfer_func color_output_tf; - struct abm_setting abm_setting; + unsigned int *abm_level; }; bool dc_is_stream_unchanged( diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index c434e38e6e46..c1a07ecd2927 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -1781,20 +1781,31 @@ static void update_dchubp_dpp( } static void dcn10_otg_blank( + struct dc *dc, struct stream_resource stream_res, - struct abm *abm, struct dc_stream_state *stream, bool blank) { + enum dc_color_space color_space; + struct tg_color black_color = {0}; + + /* program otg blank color */ + color_space = stream->output_color_space; + color_space_to_black_color(dc, color_space, &black_color); + + if (stream_res.tg->funcs->set_blank_color) + stream_res.tg->funcs->set_blank_color( + stream_res.tg, + &black_color); if (!blank) { if (stream_res.tg->funcs->set_blank) stream_res.tg->funcs->set_blank(stream_res.tg, blank); - if (abm) - abm->funcs->set_abm_level(abm, stream->abm_settings.abm_level); + if (stream_res.abm) + stream_res.abm->funcs->set_abm_level(stream_res.abm, stream->abm_level); } else if (blank) { - if (abm) - abm->funcs->set_abm_immediate_disable(abm); + if (stream_res.abm) + stream_res.abm->funcs->set_abm_immediate_disable(stream_res.abm); if (stream_res.tg->funcs->set_blank) stream_res.tg->funcs->set_blank(stream_res.tg, blank); } @@ -1817,7 +1828,7 @@ static void program_all_pipe_in_tree( pipe_ctx->stream_res.tg->funcs->program_global_sync( pipe_ctx->stream_res.tg); - dcn10_otg_blank(pipe_ctx->stream_res, dc->res_pool->abm, + dcn10_otg_blank(dc, pipe_ctx->stream_res, pipe_ctx->stream, blank); } @@ -1941,7 +1952,7 @@ static void dcn10_apply_ctx_for_surface( if (num_planes == 0) { /* OTG blank before remove all front end */ - dcn10_otg_blank(top_pipe_to_program->stream_res, dc->res_pool->abm, top_pipe_to_program->stream, true); + dcn10_otg_blank(dc, top_pipe_to_program->stream_res, top_pipe_to_program->stream, true); } /* Disconnect unused mpcc */ diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index c4a564cb56b9..617aa8ca0156 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -963,6 +963,7 @@ static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer( idle_pipe->stream = head_pipe->stream; idle_pipe->stream_res.tg = head_pipe->stream_res.tg; + idle_pipe->stream_res.abm = head_pipe->stream_res.abm; idle_pipe->stream_res.opp = head_pipe->stream_res.opp; idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx]; diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index b8f05384a897..8c51ad70cace 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -194,6 +194,8 @@ struct stream_resource { struct pixel_clk_params pix_clk_params; struct encoder_info_frame encoder_info_frame; + + struct abm *abm; }; struct plane_resource { -- cgit v1.2.3