path: root/drivers/gpu
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2018-03-21Merge airlied/drm-next into drm-misc-nextdrm-misc-next-2018-03-21Sean Paul716-32814/+67289
Refresh -misc-next Signed-off-by: Sean Paul <>
2018-03-21drm/qxl: Replace drm_gem_object_reference/unreference() with _get/put()Santha Meena Ramamoorthy6-12/+12
Replace drm_gem_object_reference/unreference function with *_get/put() suffixes, because it is shorter and consistent with the kernel kref_get/put() functions. The following Coccinelle script was used: @@ expression e; @@ ( -drm_gem_object_reference(e); +drm_gem_object_get(e); | -drm_gem_object_unreference(e); +drm_gem_object_put(e); | -drm_gem_object_unreference_unlocked(e); +drm_gem_object_put_unlocked(e); ) Signed-off-by: Santha Meena Ramamoorthy <> Signed-off-by: Daniel Vetter <> Link:
2018-03-21Merge tag 'omapdrm-4.17' of ↵Dave Airlie54-3831/+4276
git:// into drm-next omapdrm patches for v4.17 * Fix sparse warnings from omapdrm * HPD support for DVI connector * Big cleanup to remove static variables * tag 'omapdrm-4.17' of git:// (69 commits) drm/omap: fix compile error when DPI is disabled drm/omap: fix compile error when debugfs is disabled drm: omapdrm: displays: panel-dsi-cm: Fix field access before set drm/omap: cleanup color space conversion drm/omap: Allow HDMI audio setup even if we do not have video configured drm/omap: fix maximum sizes drm/omap: add writeback funcs to dispc_ops drm/omap: fix scaling limits for WB drm/omap: fix WB height with interlace drm/omap: fix WBDELAYCOUNT with interlace drm/omap: fix WBDELAYCOUNT for HDMI drm/omap: set WB channel-in in wb_setup() drm/omap: Add pclk setting case when channel is DSS_WB drm/omap: dispc: disp_wb_setup to check return code drm/omap: remove leftover enums dt-bindings: display: add HPD gpio to DVI connector drm/omap: add HPD support to connector-dvi drm/omap: Init fbdev emulation only when we have displays drm/omap: cleanup fbdev init/free drm/omap: fix omap_fbdev_free() when omap_fbdev_create() wasn't called ...
2018-03-21Merge tag 'drm-msm-next-2018-03-20' of ↵Dave Airlie71-241/+1858
git:// into drm-next Updates for 4.17. Sorry, running a bit late on this, didn't have a chance to send pull-req before heading to linaro. But it has all been in linux-next for a while. Main updates: + DSI updates from 10nm / SDM845 + fix for race condition with a3xx/a4xx fence completion irq + some refactoring/prep work for eventual a6xx support (ie. when we have a userspace) + a5xx debugfs enhancements + some mdp5 fixes/cleanups to prepare for eventually merging writeback support (ie. when we have a userspace) * tag 'drm-msm-next-2018-03-20' of git:// (36 commits) drm/msm: fix building without debugfs drm/msm/mdp5: don't pre-reserve LM's if no dual-dsi drm/msm/mdp5: add missing LM flush bits drm/msm/mdp5: print a bit more of the atomic state drm/msm/mdp5: rework CTL START signal handling drm/msm: Trigger fence completion from GPU drm/msm/dsi: fix direct caller of msm_gem_free_object() drm/msm: strip out msm_fence_cb drm/msm: rename mdp->disp drm/msm/dsi: Fix potential NULL pointer dereference in msm_dsi_modeset_init drm/msm/adreno/a5xx_debugfs: fix potential NULL pointer dereference drm/msm/dsi: Get byte_intf_clk only for versions that need it drm/msm/adreno: Use generic function to load firmware to a buffer object drm/msm/adreno: Define a list of firmware files to load per target drm/msm/adreno: Rename gpmufw to powerfw drm/msm: Pass the correct aperture end to drm_mm_init drm/msm/gpu: Set number of clocks to 0 if the list allocation fails drm/msm: Replace gem_object deprecated functions drm/msm/hdmi: fix semicolon.cocci warnings drm/msm/mdp5: Fix trailing semicolon ...
2018-03-21Merge tag 'drm/tegra/for-4.17-rc1' of ↵Dave Airlie10-114/+280
git:// into drm-next drm/tegra: Changes for v4.17-rc1 This fixes mmap() for fbdev devices by providing a custom implementation based on the KMS variant. This is a fairly exotic case these days, hence why it is not flagged for stable. There is also support for dedicating one of the overlay planes to serve as a hardware cursor on older Tegra that did support hardware cursors but not RGBA formats for it. Planes will now also export the IN_FORMATS property by supporting the various block-linear tiling modifiers for RGBA pixel formats. Other than that, there's a bit of cleanup of DMA API abuse, use of the private object infrastructure for global state (rather than subclassing atomic state objects) and an implementation of ->{begin,end}_cpu_access callbacks for PRIME exported buffers, which allow users to perform cache maintenance on these buffers. * tag 'drm/tegra/for-4.17-rc1' of git:// drm/tegra: prime: Implement ->{begin,end}_cpu_access() drm/tegra: gem: Map pages via the DMA API drm/tegra: hub: Use private object for global state drm/tegra: fb: Properly support linear modifier drm/tegra: plane: Support format modifiers drm/tegra: dc: Dedicate overlay plane to cursor on older Tegra's drm/tegra: plane: Make tegra_plane_get_overlap_index() static drm/tegra: fb: Implement ->fb_mmap() callback drm/tegra: gem: Make __tegra_gem_mmap() available more widely drm/tegra: gem: Reshuffle declarations
2018-03-21Merge branch 'for-upstream/mali-dp' of git:// into ↵Dave Airlie7-77/+189
drm-next I have accumulated some patches as we went through some internal testing for mali-dp and I was waiting for the YUV2RGB patches to land in your tree. * 'for-upstream/mali-dp' of git:// drm: mali-dp: Add YUV->RGB conversion support for video layers drm: mali-dp: Turn off CRTC vblank when removing module. drm: arm: malidp: Use drm_atomic_helper_shutdown() to disable planes on removal drm: arm: malidp: Don't destroy planes manually in error handlers drm/mali-dp: Fix malidp_atomic_commit_hw_done() for event sending. drm/arm/malidp: Disable pixel alpha blending for colors that do not have alpha drm: mali-dp: Fix bug on scaling with rotation drm/mali-dp: Don't enable scaling engine for planes that only rotate. drm: mali-dp: Uninitialized variable in malidp_se_check_scaling() drm/mali-dp: Align pitch size to be multiple of bus burst read size. drm/mali-dp: Rotated planes need a larger pitch size.
2018-03-20drm/meson: Fix potential NULL dereference in meson_drv_bind_master()Wei Yongjun1-0/+4
platform_get_resource_byname() may fail and return NULL, so we should better check it's return value to avoid a NULL pointer dereference a bit later in the code. This is detected by Coccinelle semantic patch. @@ expression pdev, res, n, t, e, e1, e2; @@ res = platform_get_resource_byname(pdev, t, n); + if (!res) + return -EINVAL; ... when != res == NULL e = devm_ioremap(e1, res->start, e2); Signed-off-by: Wei Yongjun <> Signed-off-by: Neil Armstrong <> Acked-by: Neil Armstrong <> Link:
2018-03-19drm/sun4i: backend: Support YUV planesMaxime Ripard3-0/+119
Now that we have the guarantee that we will have only a single YUV plane, actually support them. The way it works is not really straightforward, since we first need to enable the YUV mode in the plane that we want to setup, and then we have a few registers to setup the YUV buffer and parameters. We also need to setup the color correction to actually have something displayed. Reviewed-by: Chen-Yu Tsai <> Signed-off-by: Maxime Ripard <> Link:
2018-03-19drm/sun4i: backend: Check that we only have a single YUV planeMaxime Ripard2-2/+48
Just like for the frontend, a single plane can use a YUV format. Make sure we have that constraint covered in our atomic_check. This is preliminary to the actual YUV support to make sure we don't end up in an impossible to support situation. Reviewed-by: Chen-Yu Tsai <> Signed-off-by: Maxime Ripard <> Link:
2018-03-19drm/sun4i: Add driver support for A80 display pipelineChen-Yu Tsai3-2/+18
This patch adds support for the compatible strings of the A80 display pipeline. Signed-off-by: Chen-Yu Tsai <> Signed-off-by: Maxime Ripard <> Link:
2018-03-19drm/sun4i: Add support for A80 TCONsChen-Yu Tsai2-0/+28
The Allwinner A80 SoC has 2 documented TCONs. The display pipeline diagram from the user manual shows a third TCON, but it's missing an interrupt line, and its registers are not explained either. It's also not used in Allwinner's vendor BSP. The first TCON only has channel 0, for LCD panel output. The TCON hardware setup is peculiar in that the eDP reset must also be deasserted to allow access to the TCON. How the eDP module is wired in the SoC itself is never explained. The second TCON only has channel 1, and its output is connected to the HDMI encoder block. This patch adds a "needs_edp_reset" field to the tcon quirks structure, and adds quirks and compatible strings for the 2 documented TCONs. Signed-off-by: Chen-Yu Tsai <> Signed-off-by: Maxime Ripard <> Link:
2018-03-19drm: Reduce object size of DRM_DEV_<LEVEL> usesJoe Perches1-9/+28
These macros are similar to the DRM_<LEVEL> with the addition of a struct device * to the arguments. Convert the single drm_dev_printk function into 2 separate functions. drm_dev_printk with a KERN_<LEVEL> * for generic use and drm_dev_dbg for conditional masked use. Remove the __func__ argument and use __builtin_return_address(0) to be similar to the DRM_<LEVEL> macros uses. Convert the DRM_DEV_<LEVEL> macros to remove now unnecessary arguments and use a consistent style. These macros are rarely used in the generic gpu/drm code so the code size does not change much for a defconfig, but when more drivers are enabled, there is ~4k savings. Many of these macros have no existing use at all. $ size -t drivers/gpu/drm/built-in.a | tail -1 1877530 44651 995 1923176 1d5868 (TOTALS) $ size -t drivers/gpu/drm/built-in.a | tail -1 1877527 44651 995 1923173 1d5865 (TOTALS) $ size -t drivers/gpu/drm/built-in.a | tail -1 17166750 2689238 108352 19964340 130a1b4 (TOTALS) $ size -t drivers/gpu/drm/built-in.a | tail -1 17168888 2691734 108352 19968974 130b3ce (TOTALS) Signed-off-by: Joe Perches <> Signed-off-by: Daniel Vetter <> Link:
2018-03-19drm: dma_bufs: Fixed checkpatch issuesPaul McQuade1-8/+8
Fix a couple of checkpatch issues Signed-off-by: Paul McQuade <> [seanpaul squashed series of 4 into one patch, and changed commit msg] Signed-off-by: Sean Paul <> Link:
2018-03-19drm/msm: fix building without debugfsArnd Bergmann1-0/+2
The adreno driver stopped building when CONFIG_DEBUGFS is disabled: drivers/gpu/drm/msm/adreno/adreno_device.c: In function 'adreno_load_gpu': drivers/gpu/drm/msm/adreno/adreno_device.c:153:16: error: 'const struct msm_gpu_funcs' has no member named 'debugfs_init' if (gpu->funcs->debugfs_init) { ^~ drivers/gpu/drm/msm/adreno/adreno_device.c:154:13: error: 'const struct msm_gpu_funcs' has no member named 'debugfs_init' gpu->funcs->debugfs_init(gpu, dev->primary); ^~ This adds an #ifdef around the code that references the hidden pointer. Fixes: 331dc0bc195b ("drm/msm: add a5xx specific debugfs") Signed-off-by: Arnd Bergmann <> Signed-off-by: Rob Clark <>
2018-03-19drm/msm/mdp5: don't pre-reserve LM's if no dual-dsiRob Clark1-1/+5
If there is only a single DSI interface, don't reserve the first two layer-mixers for the dual-DSI use-case. This was causing problems for WB, not being able to assign a LM, on 8x16, which has only two LM's and a single DSI. Signed-off-by: Rob Clark <>
2018-03-19drm/msm/mdp5: add missing LM flush bitsRob Clark1-0/+2
For some reason, layer-mixer 3 and 4 were missing. LM3 is used for writeback on 8x16. Signed-off-by: Rob Clark <>
2018-03-19drm/msm/mdp5: print a bit more of the atomic stateRob Clark1-0/+5
Signed-off-by: Rob Clark <>
2018-03-19drm/msm/mdp5: rework CTL START signal handlingRob Clark7-44/+35
For DSI cmd-mode and writeback, we need to write the CTL's START register to kick things off, but we only want to do that once both the encoder and the crtc have a chance to write their corresponding flush bits. The difficulty is that when there is a full modeset (ie. encoder state has changed) we want to defer the start until encoder->enable(). But if only plane's have changed, we want to do this from crtc->commit(). The start_mask was a previous attempt to handle this, but it didn't really do the right thing since atomic conversion. Instead track in the crtc state that the start should be deferred, set to try from encoder's (or in future writeback's) atomic_check(). This way the state is part of the atomic state, and rollback can work properly if an atomic test fails. Signed-off-by: Rob Clark <>
2018-03-19drm/msm: Trigger fence completion from GPUBjorn Andersson3-16/+4
Interrupt commands causes the CP to trigger an interrupt as the command is processed, regardless of the GPU being done processing previous commands. This is seen by the interrupt being delivered before the fence is written on 8974 and is likely the cause of the additional CP_WAIT_FOR_IDLE workaround found for a306, which would cause the CP to wait for the GPU to go idle before triggering the interrupt. Instead we can set the (undocumented) BIT(31) of the CACHE_FLUSH_TS which will cause a special CACHE_FLUSH_TS interrupt to be triggered from the GPU as the write event is processed. Add CACHE_FLUSH_TS to the IRQ masks of A3xx and A4xx and remove the workaround for A306. Suggested-by: Jordan Crouse <> Signed-off-by: Bjorn Andersson <> Signed-off-by: Rob Clark <>
2018-03-19drm/msm/dsi: fix direct caller of msm_gem_free_object()Rob Clark2-3/+2
This should be using drm_gem_object_put(). Also since this is done only in driver unload path, we don't need to synchronize setting tx_gem_obj to NULL, so juse use the _unlocked() variant. Signed-off-by: Rob Clark <>
2018-03-19drm/msm: strip out msm_fence_cbRob Clark2-3/+0
Remnants of pre-dma_fence fencing which got left behind by mistake. Signed-off-by: Rob Clark <>
2018-03-19drm/msm: rename mdp->dispRob Clark35-25/+25
Since new display controller is called "dpu" instead of "mdp". Lets make the name of the toplevel directory for the display controllers a bit more generic. Signed-off-by: Rob Clark <> Reviewed-by: Sean Paul <>
2018-03-19drm/msm/dsi: Fix potential NULL pointer dereference in msm_dsi_modeset_initGustavo A. R. Silva1-1/+2
_dev_ is being dereferenced before it is null checked, hence there is a potential null pointer dereference. Fix this by moving the pointer dereference after _dev_ has been null checked. Fixes: d4e7f38d70ef ("drm/msm/dsi: check msm_dsi and dsi pointers before use") Signed-off-by: Gustavo A. R. Silva <> Signed-off-by: Rob Clark <>
2018-03-19drm/msm/adreno/a5xx_debugfs: fix potential NULL pointer dereferenceGustavo A. R. Silva1-1/+3
_minor_ is being dereferenced before it is null checked, hence there is a potential null pointer dereference. Fix this by moving the pointer dereference after _minor_ has been null checked. Fixes: 024ad8df763f ("drm/msm: add a5xx specific debugfs") Signed-off-by: Gustavo A. R. Silva <> Signed-off-by: Rob Clark <>
2018-03-17drm/tegra: prime: Implement ->{begin,end}_cpu_access()Thierry Reding1-0/+30
These callbacks allow the exporter to swap in and pin the backing storage for buffers as well as invalidate the cache in preparation for accessing the buffer from the CPU, and flush the cache and unpin the backing storage when the CPU is done modifying the buffer. Signed-off-by: Thierry Reding <>
2018-03-17drm/tegra: gem: Map pages via the DMA APIThierry Reding1-16/+16
When allocating pages, map them with the DMA API in order to invalidate caches. This is the correct usage of the API and works just as well as faking up the SG table and using the dma_sync_sg_for_device() function. Signed-off-by: Thierry Reding <>
2018-03-17drm/tegra: hub: Use private object for global stateThierry Reding5-80/+123
Rather than subclass the global atomic state to store the hub display clock and rate, create a private object and store this data in its state. Signed-off-by: Thierry Reding <>
2018-03-16drm/vc4_validate: Remove VLA usageGustavo A. R. Silva1-1/+1
In preparation to enabling -Wvla, remove VLA. In this particular case use macro ARRAY_SIZE so the length of array _bo_ can be computed at preprocessing time. The use of stack Variable Length Arrays needs to be avoided, as they can be a vector for stack exhaustion, which can be both a runtime bug or a security flaw. Also, in general, as code evolves it is easy to lose track of how big a VLA can get. Thus, we can end up having runtime failures that are hard to debug. Also, fixed as part of the directive to remove all VLAs from the kernel: Signed-off-by: Gustavo A. R. Silva <> Signed-off-by: Eric Anholt <> Reviewed-by: Eric Anholt <> Link:
2018-03-16amdgpu/dm: Default PRE_VEGA ASIC support to 'y'Harry Wentland1-1/+1
Even though we default PRE_VEGA support to 'n' upstream in amd-staging we want to keep it enabled by default. Signed-off-by: Harry Wentland <> Reviewed-by: Alex Deucher <> Signed-off-by: Alex Deucher <>
2018-03-16drm/amd/pp: Remove the cgs wrapper for notify smu version on APURex Zhu3-12/+5
Refine commit f49e9bac191b ("drm/amd/pp: Get and save Rv smu version") Reviewed-by: Alex Deucher <> Signed-off-by: Rex Zhu <> Signed-off-by: Alex Deucher <>
2018-03-16drm/amd/display: fix dereferencing possible ERR_PTR()Shirish S1-0/+3
This patch fixes static checker warning caused by "36cc549d5986: "drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)" Reported-by: Dan Carpenter <> Signed-off-by: Shirish S <> Reviewed-by: Harry Wentland <> Acked-by: Alex Deucher <> Signed-off-by: Alex Deucher <>
2018-03-16drm/amd/display: Refine disable VGAClark Zheng2-6/+22
bad case won't follow normal sense, it will not enable vga1 as usual, but vga2,3,4 is on. Signed-off-by: Clark Zheng <> Reviewed-by: Tony Cheng <> Acked-by: Alex Deucher <> Signed-off-by: Alex Deucher <>
2018-03-16drm: Make drm_mode_vrefresh() a bit more accurateVille Syrjälä1-10/+9
Do the refresh rate calculation with a single division. This gives us slightly more accurate results, especially for interlaced since we don't just double the final truncated result. We do lose one bit compared to the old way, so with an interlaced mode the new code can only handle ~2GHz instead of the ~4GHz the old code handeled. Signed-off-by: Ville Syrjälä <> Link: Reviewed-by: Daniel Vetter <>
2018-03-16drm: Nuke the useless 'ret' variable from drm_mode_convert_umode()Ville Syrjälä1-11/+4
No need to store the return value in a variable since we don't have to do any unwinding. Signed-off-by: Ville Syrjälä <> Link: Reviewed-by: Daniel Vetter <>
2018-03-16drm/i915: Use drm_color_lut_size()Ville Syrjälä1-8/+6
Avoid all the sizeof(drm_color_lut) business by using drm_color_lut_size() to convert the blob length into number of LUT entries. Signed-off-by: Ville Syrjälä <> Link: Reviewed-by: Daniel Vetter <>
2018-03-16drm/i915: Remove the blob->data castsVille Syrjälä1-11/+7
Now that blob->data is void* again we don't need to cast it. Signed-off-by: Ville Syrjälä <> Link: Reviewed-by: Daniel Vetter <>
2018-03-16drm: Verify gamma/degamma LUT sizeVille Syrjälä1-4/+35
While we want to potentially support multiple different gamma/degamma LUT sizes we can (and should) at least check that the blob length is a multiple of the LUT entry size. v2: s/expected_size_mod/expected_elem_size/ (Daniel) Add kernel doc (Daniel) v3: s/we/were/ typo in the docs Cc: Daniel Vetter <> Signed-off-by: Ville Syrjälä <> Reviewed-by: Daniel Vetter <> Link:
2018-03-16drm: Remove now pointelss blob->data castsVille Syrjälä5-7/+5
Now that blob->data is void* again we don't need the casts anymore. Signed-off-by: Ville Syrjälä <> Link: Reviewed-by: Shashank Sharma <> Reviewed-by: Daniel Vetter <>
2018-03-16Revert "drm: Use a flexible array member for blob property data"Ville Syrjälä1-0/+1
Using a flexible array for the blob data was a mistake by me. It forces all users of the blob data to cast blob->data to something else. void* is clearly superior so let's go back to the original scheme. Not a clean revert as the code has moved. This reverts commit d63f5e6bf6f2a1573ea39c9937cdf5ab0b3a4b77. Signed-off-by: Ville Syrjälä <> Link: Reviewed-by: Shashank Sharma <> Reviewed-by: Daniel Vetter <>
2018-03-16drm/rockchip: cdn-dp: remove the DP phy switchChris Zhong1-7/+0
There are 2 Type-c PHYs in RK3399, but only one DP controller. Hence only one PHY can connect to DP controller at one time, the other should be disconnected. The GRF_SOC_CON26 register has a switch bit to do it, set this bit means enable PHY 1, clear this bit means enable PHY 0. If the board has 2 Type-C ports, the DP driver get the phy id from devm_of_phy_get_by_index, and then control this switch according to this id. But some others board only has one Type-C port, it may be PHY 0 or PHY 1. The dts node id can not tell us the correct PHY id. Hence move this switch to PHY driver, the PHY driver can distinguish between PHY 0 and PHY 1, and then write the correct register bit. Signed-off-by: Chris Zhong <> Signed-off-by: Enric Balletbo i Serra <> [The phy-changes are in the phy-tree now and the cdn-dp wasn't enabled at all so far, so this change can go through drm-misc alone without causing issues when testing drm-misc] Signed-off-by: Heiko Stuebner <> Link:
2018-03-16drm: Reduce object size of DRM_ERROR and DRM_DEBUG usesJoe Perches2-18/+25
drm_printk is used for both DRM_ERROR and DRM_DEBUG with unnecessary arguments that can be removed by creating separate functins. Create specific functions for these calls to reduce x86/64 defconfig size by ~20k. Modify the existing macros to use the specific calls. new: $ size -t drivers/gpu/drm/built-in.a | tail -1 1876562 44542 995 1922099 1d5433 (TOTALS) old: $ size -t drivers/gpu/drm/built-in.a | tail -1 1897565 44542 995 1943102 1da63e (TOTALS) Miscellanea: o intel_display requires a change to use the specific calls. Signed-off-by: Joe Perches <> Signed-off-by: Daniel Vetter <> Link:
2018-03-15drm/amdgpu: Improve documentation of bo_ptr in amdgpu_bo_create_kernelAndrey Grodzovsky1-2/+6
and amdgpu_bo_create_reserved. Signed-off-by: Andrey Grodzovsky <> Reviewed-by: Alex Deucher <> Reviewed-by: Christian König <> Signed-off-by: Alex Deucher <>
2018-03-15drm/tegra: fb: Properly support linear modifierThierry Reding1-3/+6
Instead of relying on the tiling attached to a buffer object, make sure to set the proper tiling for linear buffers. Signed-off-by: Thierry Reding <>
2018-03-15drm/tegra: plane: Support format modifiersThierry Reding4-2/+56
Pass the list of valid format modifiers to planes upon initialization and implement the ->format_mod_supported() callback so that userspace can query for the valid combinations of formats and modifiers. Signed-off-by: Thierry Reding <>
2018-03-15drm/radeon: Don't turn off DP sink when disconnectedMichel Dänzer1-19/+12
Turning off the sink in this case causes various issues, because userspace expects it to stay on until it turns it off explicitly. Instead, turn the sink off and back on when a display is connected again. This dance seems necessary for link training to work correctly. Bugzilla: Cc: Reviewed-by: Alex Deucher <> Signed-off-by: Michel Dänzer <> Signed-off-by: Alex Deucher <>
2018-03-15drm/amd/pp: Rename file name cz_* to smu8_*Rex Zhu6-4/+4
Reviewed-by: Alex Deucher <> Reviewed-by: Evan Quan <> Signed-off-by: Rex Zhu <> Signed-off-by: Alex Deucher <>
2018-03-15drm/amd/pp: Replace function/struct name cz_* with smu8_*Rex Zhu5-807/+806
hw ip smu8 was used on CZ/ST, so use smu8 as the prefix of the function/struct name in powerplay. Reviewed-by: Alex Deucher <> Reviewed-by: Evan Quan <> Signed-off-by: Rex Zhu <> Signed-off-by: Alex Deucher <>
2018-03-15drm/amd/pp: Remove unneeded void * casts in cz_hwmgr.c/cz_smumgr.cRex Zhu2-60/+60
Removes unneeded void * casts for the following pointers: hwmgr->backend hwmgr->smu_backend Reviewed-by: Alex Deucher <> Reviewed-by: Evan Quan <> Signed-off-by: Rex Zhu <> Signed-off-by: Alex Deucher <>
2018-03-15drm/amd/pp: Mv cz uvd/vce pg/dpm functions to cz_hwmgr.cRex Zhu5-209/+140
1. delete cz_clockpowergating.c/.h files 2. mark uvd/vce dpm/pg functions static Reviewed-by: Alex Deucher <> Reviewed-by: Evan Quan <> Signed-off-by: Rex Zhu <> Signed-off-by: Alex Deucher <>
2018-03-15drm/amd/pp: Remove dead header file pp_asicblocks.hRex Zhu2-48/+0
Reviewed-by: Alex Deucher <> Reviewed-by: Evan Quan <> Signed-off-by: Rex Zhu <> Signed-off-by: Alex Deucher <>